diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v b/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
index 688ff92..965c894 100644
--- a/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
@@ -1,9 +1,9 @@
 module top_uart_ultrason_command (
-    input wire clk, // 27 MHz
+    input wire  clk, // 27 MHz
     output wire tx,
-    input wire rx,
-    inout wire ultrason_sig, // Capteur ultrason
-    output reg [5:0] leds
+    input wire  rx,
+    inout wire  ultrason_sig, // Capteur ultrason
+    output reg  [5:0] leds
 );
 
     // === UART RX WIRE ===
@@ -66,7 +66,8 @@ module top_uart_ultrason_command (
 
     always @(posedge clk) begin
         
-        leds [4] <= tx;
+        leds [4] <= data_available;
+
         case (rx_state)
             IDLE: begin
                 leds [5] <= 0;