From cd14d82add9d6d40739db225604282d5b94ef32b Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Fri, 9 May 2025 09:20:56 +0200 Subject: [PATCH] patch --- Semaine_4/UART/src/verilog/top_uart_loopback1.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Semaine_4/UART/src/verilog/top_uart_loopback1.v b/Semaine_4/UART/src/verilog/top_uart_loopback1.v index 378ccf8..ac08270 100644 --- a/Semaine_4/UART/src/verilog/top_uart_loopback1.v +++ b/Semaine_4/UART/src/verilog/top_uart_loopback1.v @@ -118,6 +118,7 @@ localparam DATA_BYTE = 8'h31; // ASCII '1' begin // Default assignments tx_enable <= 1'b0; + leds[5:0] <= rx_data[5:0]; if (tx_ready && delay_counter == 0) begin // Start new transmission @@ -125,7 +126,7 @@ localparam DATA_BYTE = 8'h31; // ASCII '1' data_const <= DATA_BYTE; tx_data <= rx_data; - leds[5:0] <= rx_data[5:0]; // Display received data on LEDs + // Display received data on LEDs delay_counter <= DELAY_CYCLES; end