From d69a0a47530890de43e3432add28ef592e2b497d Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Tue, 27 May 2025 13:38:33 +0200 Subject: [PATCH] Adjust timer threshold for signal detection in DHT11 interface --- Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v b/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v index a77af95..819b4bc 100644 --- a/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v +++ b/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v @@ -107,7 +107,7 @@ module dht11_interface #( timer <= timer + 1; - if (sig_in == 0 && timer > 1) begin + if (sig_in == 0 && timer > 2) begin state <= RESPONSE_LOW; timer <= 0; @@ -119,7 +119,7 @@ module dht11_interface #( o_state <= state; timer <= timer + 1; - if (sig_in == 1) begin + if (sig_in == 1 && timer > 2) begin timer <= 0; state <= RESPONSE_HIGH;