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Refactor ultrasonic FPGA module: replace sig_in with sig_ok for improved signal handling and update ESP32 command processing to support new client list command

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Gamenight77
2025-04-25 09:17:22 +02:00
parent f2bcd7bc24
commit d8708d1bd5
3 changed files with 82 additions and 12 deletions
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9
Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v
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@@ -13,7 +13,10 @@ module ultrasonic_fpga #(
reg sig_dir; // 1: output, 0: input
assign sig = sig_dir ? sig_out : 1'bz; // bz pour dire que le fpga laisse le fils libre et n'oblige pas de valeur
wire sig_in = sig;
reg sig_int, sig_ok;
always_ff(@posedge clk) {sig_ok, sig_int} = {sig_int, sig};
localparam IDLE = 3'd0,
TRIG_HIGH = 3'd1,
@@ -65,7 +68,7 @@ module ultrasonic_fpga #(
end
WAIT_ECHO: begin
if (sig_in) begin
if (sig_ok) begin
echo_counter <= 0;
state <= MEASURE_ECHO;
end else if (echo_counter >= TIMEOUT_CYCLES) begin
@@ -77,7 +80,7 @@ module ultrasonic_fpga #(
end
MEASURE_ECHO: begin
if (sig_in) begin
if (sig_ok) begin
if (echo_counter < TIMEOUT_CYCLES) begin
echo_counter <= echo_counter + 1;
end else begin