From e086ba8ef0d87887fe9a3cc31c8162260de993b1 Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Fri, 9 May 2025 11:39:40 +0200 Subject: [PATCH] =?UTF-8?q?Loopback=20fifo=20fonctionne=20mais=20avec=203?= =?UTF-8?q?=20valeur=20de=20d=C3=A9calage?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- README.md | 2 +- Semaine_4/UART_FIFO/IP/verilog/fifo.v | 18 +- Semaine_4/UART_FIFO/IP/verilog/rxuartlite.v | 796 ++++++++++++++++++ Semaine_4/UART_FIFO/scripts/build.bat | 2 +- Semaine_4/UART_FIFO/scripts/gtkwave.bat | 2 +- Semaine_4/UART_FIFO/scripts/simulate.bat | 2 +- .../src/verilog/top_uart_loopback_fifo.v | 62 +- .../UART_FIFO/src/verilog/uart_rx_fifo.v | 22 +- .../UART_FIFO/src/verilog/uart_tx_fifo.v | 4 +- .../UART_FIFO/tests/verilog/tb_uart_fifo.v | 54 +- Semaine_5/UART_ULTRASON_COMMANDS/.gitignore | 4 + .../UART_ULTRASON_COMMANDS/IP/verilog/fifo.v | 43 + .../IP/verilog/uart_tx.v | 131 +++ .../IP/verilog/uart_tx_fifo.v | 86 ++ .../IP/verilog/ultrasonic_fpga.v | 151 ++++ Semaine_5/UART_ULTRASON_COMMANDS/README.md | 9 + .../constraints/top_uart_ultrason.cst | 9 + Semaine_5/UART_ULTRASON_COMMANDS/project.bat | 6 + .../UART_ULTRASON_COMMANDS/scripts/build.bat | 45 + .../UART_ULTRASON_COMMANDS/scripts/clean.bat | 4 + .../scripts/gtkwave.bat | 3 + .../scripts/simulate.bat | 29 + .../src/verilog/top_uart_ultrason.v | 81 ++ .../tests/Python/uart_ultrason_receiver.py | 21 + .../tests/verilog/tb_uart_ultrason.v | 84 ++ 25 files changed, 1578 insertions(+), 92 deletions(-) create mode 100644 Semaine_4/UART_FIFO/IP/verilog/rxuartlite.v create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/.gitignore create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx.v create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx_fifo.v create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_fpga.v create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/README.md create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason.cst create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/project.bat create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/scripts/build.bat create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/scripts/clean.bat create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/scripts/gtkwave.bat create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/scripts/simulate.bat create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason.v create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/uart_ultrason_receiver.py create mode 100644 Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v diff --git a/README.md b/README.md index c4c5aaf..cf57cd0 100644 --- a/README.md +++ b/README.md @@ -13,7 +13,7 @@ - Transformer le rd_data en registre et la mettre à jour dans le posedge clk - +* Nouveau RX FIFO avec le rxuartlite * Tester UART FIFO avec délais diff --git a/Semaine_4/UART_FIFO/IP/verilog/fifo.v b/Semaine_4/UART_FIFO/IP/verilog/fifo.v index a67914e..031be59 100644 --- a/Semaine_4/UART_FIFO/IP/verilog/fifo.v +++ b/Semaine_4/UART_FIFO/IP/verilog/fifo.v @@ -1,25 +1,24 @@ module fifo #( - parameter DEPTH = 16, + parameter SIZE = 16, parameter WIDTH = 8 )( input wire clk, input wire wr_en, input wire[WIDTH-1:0] wr_data, input wire rd_en, - output wire[WIDTH-1:0] rd_data, + output reg[WIDTH-1:0] rd_data, output wire full, output wire empty ); - reg [WIDTH-1:0] fifo[0:DEPTH-1]; + reg [WIDTH-1:0] fifo[0:SIZE-1]; reg [3:0] wr_ptr; reg [3:0] rd_ptr; reg [3:0] count; - assign full = (count == DEPTH); + assign full = (count == SIZE); assign empty = (count == 0); - assign rd_data = fifo[rd_ptr]; initial begin wr_ptr = 0; @@ -27,15 +26,16 @@ count = 0; end - always @(posedge clk) begin + always @(posedge clk) begin // IN if (wr_en && !full) begin fifo[wr_ptr] <= wr_data; - wr_ptr <= (wr_ptr + 1) % DEPTH; + wr_ptr <= (wr_ptr + 1) % SIZE; count <= count + 1; end - if (rd_en && !empty) begin - rd_ptr <= (rd_ptr + 1) % DEPTH; + if (rd_en && !empty) begin // OUT + rd_ptr <= (rd_ptr + 1) % SIZE; + rd_data <= fifo[rd_ptr]; count <= count - 1; end end diff --git a/Semaine_4/UART_FIFO/IP/verilog/rxuartlite.v b/Semaine_4/UART_FIFO/IP/verilog/rxuartlite.v new file mode 100644 index 0000000..a527848 --- /dev/null +++ b/Semaine_4/UART_FIFO/IP/verilog/rxuartlite.v @@ -0,0 +1,796 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// Filename: rxuartlite.v +// {{{ +// Project: wbuart32, a full featured UART with simulator +// +// Purpose: Receive and decode inputs from a single UART line. +// +// +// To interface with this module, connect it to your system clock, +// and a UART input. Set the parameter to the number of clocks per +// baud. When data becomes available, the o_wr line will be asserted +// for one clock cycle. +// +// This interface only handles 8N1 serial port communications. It does +// not handle the break, parity, or frame error conditions. +// +// +// Creator: Dan Gisselquist, Ph.D. +// Gisselquist Technology, LLC +// +//////////////////////////////////////////////////////////////////////////////// +// }}} +// Copyright (C) 2015-2024, Gisselquist Technology, LLC +// {{{ +// This program is free software (firmware): you can redistribute it and/or +// modify it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or (at +// your option) any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program. (It's in the $(ROOT)/doc directory. Run make with no +// target there if the PDF file isn't present.) If not, see +// for a copy. +// }}} +// License: GPL, v3, as defined and found on www.gnu.org, +// {{{ +// http://www.gnu.org/licenses/gpl.html +// +//////////////////////////////////////////////////////////////////////////////// +// +`default_nettype none +// }}} +module rxuartlite #( + // {{{ + parameter TIMER_BITS = 10, +`ifdef FORMAL + parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof +`else + parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 234, // 115200 Baud at 100MHz +`endif + localparam TB = TIMER_BITS, + // + localparam [3:0] RXUL_BIT_ZERO = 4'h0, + // Verilator lint_off UNUSED + // These are used by the formal solver + localparam [3:0] RXUL_BIT_ONE = 4'h1, + localparam [3:0] RXUL_BIT_TWO = 4'h2, + localparam [3:0] RXUL_BIT_THREE = 4'h3, + localparam [3:0] RXUL_BIT_FOUR = 4'h4, + localparam [3:0] RXUL_BIT_FIVE = 4'h5, + localparam [3:0] RXUL_BIT_SIX = 4'h6, + localparam [3:0] RXUL_BIT_SEVEN = 4'h7, + // Verilator lint_on UNUSED + localparam [3:0] RXUL_STOP = 4'h8, + localparam [3:0] RXUL_WAIT = 4'h9, + localparam [3:0] RXUL_IDLE = 4'hf + // }}} + ) ( + // {{{ + input wire i_clk, i_reset, + input wire i_uart_rx, + output reg o_wr, + output reg [7:0] o_data + // }}} + ); + + // Signal/register declarations + // {{{ + wire [(TB-1):0] half_baud; + reg [3:0] state; + + assign half_baud = { 1'b0, CLOCKS_PER_BAUD[(TB-1):1] }; + reg [(TB-1):0] baud_counter; + reg zero_baud_counter; + + reg q_uart, qq_uart, ck_uart; + reg [(TB-1):0] chg_counter; + reg half_baud_time; + reg [7:0] data_reg; + // }}} + + // ck_uart + // {{{ + // Since this is an asynchronous receiver, we need to register our + // input a couple of clocks over to avoid any problems with + // metastability. We do that here, and then ignore all but the + // ck_uart wire. + initial q_uart = 1'b1; + initial qq_uart = 1'b1; + initial ck_uart = 1'b1; + always @(posedge i_clk) + if (i_reset) + { ck_uart, qq_uart, q_uart } <= 3'b111; + else + { ck_uart, qq_uart, q_uart } <= { qq_uart, q_uart, i_uart_rx }; + // }}} + + // chg_counter + // {{{ + // Keep track of the number of clocks since the last change. + // + // This is used to determine if we are in either a break or an idle + // condition, as discussed further below. + initial chg_counter = {(TB){1'b1}}; + always @(posedge i_clk) + if (i_reset) + chg_counter <= {(TB){1'b1}}; + else if (qq_uart != ck_uart) + chg_counter <= 0; + else if (chg_counter != { (TB){1'b1} }) + chg_counter <= chg_counter + 1; + // }}} + + // half_baud_time + // {{{ + // Are we in the middle of a baud iterval? Specifically, are we + // in the middle of a start bit? Set this to high if so. We'll use + // this within our state machine to transition out of the IDLE + // state. + initial half_baud_time = 0; + always @(posedge i_clk) + if (i_reset) + half_baud_time <= 0; + else + half_baud_time <= (!ck_uart)&&(chg_counter >= half_baud-1'b1-1'b1); + // }}} + + // state + // {{{ + initial state = RXUL_IDLE; + always @(posedge i_clk) + if (i_reset) + begin + state <= RXUL_IDLE; + end else if (state == RXUL_IDLE) + begin // Idle state, independent of baud counter + // {{{ + // By default, just stay in the IDLE state + state <= RXUL_IDLE; + if ((!ck_uart)&&(half_baud_time)) + // UNLESS: We are in the center of a valid + // start bit + state <= RXUL_BIT_ZERO; + // }}} + end else if ((state >= RXUL_WAIT)&&(ck_uart)) + state <= RXUL_IDLE; + else if (zero_baud_counter) + begin + // {{{ + if (state <= RXUL_STOP) + // Data arrives least significant bit first. + // By the time this is clocked in, it's what + // you'll have. + state <= state + 1; + // }}} + end + // }}} + + // data_reg + // {{{ + // Data bit capture logic. + // + // This is drastically simplified from the state machine above, based + // upon: 1) it doesn't matter what it is until the end of a captured + // byte, and 2) the data register will flush itself of any invalid + // data in all other cases. Hence, let's keep it real simple. + always @(posedge i_clk) + if ((zero_baud_counter)&&(state != RXUL_STOP)) + data_reg <= { qq_uart, data_reg[7:1] }; + // }}} + + // o_wr, o_data + // {{{ + // Our data bit logic doesn't need nearly the complexity of all that + // work above. Indeed, we only need to know if we are at the end of + // a stop bit, in which case we copy the data_reg into our output + // data register, o_data, and tell others (for one clock) that data is + // available. + // + initial o_wr = 1'b0; + initial o_data = 8'h00; + always @(posedge i_clk) + if (i_reset) + begin + o_wr <= 1'b0; + o_data <= 8'h00; + end else if ((zero_baud_counter)&&(state == RXUL_STOP)&&(ck_uart)) + begin + o_wr <= 1'b1; + o_data <= data_reg; + end else + o_wr <= 1'b0; + // }}} + + // baud_counter -- The baud counter + // {{{ + // This is used as a "clock divider" if you will, but the clock needs + // to be reset before any byte can be decoded. In all other respects, + // we set ourselves up for CLOCKS_PER_BAUD counts between baud + // intervals. + initial baud_counter = 0; + always @(posedge i_clk) + if (i_reset) + baud_counter <= 0; + else if (((state==RXUL_IDLE))&&(!ck_uart)&&(half_baud_time)) + baud_counter <= CLOCKS_PER_BAUD-1'b1; + else if (state == RXUL_WAIT) + baud_counter <= 0; + else if ((zero_baud_counter)&&(state < RXUL_STOP)) + baud_counter <= CLOCKS_PER_BAUD-1'b1; + else if (!zero_baud_counter) + baud_counter <= baud_counter-1'b1; + // }}} + + // zero_baud_counter + // {{{ + // Rather than testing whether or not (baud_counter == 0) within our + // (already too complicated) state transition tables, we use + // zero_baud_counter to pre-charge that test on the clock + // before--cleaning up some otherwise difficult timing dependencies. + initial zero_baud_counter = 1'b1; + always @(posedge i_clk) + if (i_reset) + zero_baud_counter <= 1'b1; + else if ((state == RXUL_IDLE)&&(!ck_uart)&&(half_baud_time)) + zero_baud_counter <= 1'b0; + else if (state == RXUL_WAIT) + zero_baud_counter <= 1'b1; + else if ((zero_baud_counter)&&(state < RXUL_STOP)) + zero_baud_counter <= 1'b0; + else if (baud_counter == 1) + zero_baud_counter <= 1'b1; + // }}} +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// +// Formal properties +// {{{ +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + // Declarations + // {{{ +`ifdef FORMAL +`define FORMAL_VERILATOR +`else +`ifdef VERILATOR +`define FORMAL_VERILATOR +`endif +`endif + +`ifdef FORMAL + localparam F_CKRES = 10; + + (* anyseq *) wire f_tx_start; + (* anyconst *) wire [(F_CKRES-1):0] f_tx_step; + (* gclk *) wire gbl_clk; + reg f_tx_zclk; + reg [(TB-1):0] f_tx_timer; + wire [7:0] f_rx_newdata; + reg [TB-1:0] f_tx_baud; + wire f_tx_zbaud; + + wire [(TB-1):0] f_max_baud_difference; + reg [(TB-1):0] f_baud_difference; + reg [(TB+3):0] f_tx_count, f_rx_count; + (* anyseq *) wire [7:0] f_tx_data; + + wire f_txclk; + reg [1:0] f_rx_clock; + reg [(F_CKRES-1):0] f_tx_clock; + reg f_past_valid, f_past_valid_tx; + + reg [9:0] f_tx_reg; + reg f_tx_busy; + + // }}} + + initial f_past_valid = 1'b0; + always @(posedge i_clk) + f_past_valid <= 1'b1; + + initial f_rx_clock = 3'h0; + always @(posedge gbl_clk) + f_rx_clock <= f_rx_clock + 1'b1; + + always @(*) + assume(i_clk == f_rx_clock[1]); + + always @(posedge gbl_clk) + if (!$rose(i_clk)) + assume(!$fell(i_reset)); + + + //////////////////////////////////////////////////////////////////////// + // + // Assume a transmitted signal + // {{{ + //////////////////////////////////////////////////////////////////////// + // + // + + // First, calculate the transmit clock + localparam [(F_CKRES-1):0] F_MIDSTEP = { 2'b01, {(F_CKRES-2){1'b0}} }; + // + // Need to allow us to slip by half a baud clock over 10 baud intervals + // + // (F_STEP / (2^F_CKRES)) * (CLOCKS_PER_BAUD)*10 < CLOCKS_PER_BAUD/2 + // F_STEP * 2 * 10 < 2^F_CKRES + localparam [(F_CKRES-1):0] F_HALFSTEP= F_MIDSTEP/32; + localparam [(F_CKRES-1):0] F_MINSTEP = F_MIDSTEP - F_HALFSTEP + 1; + localparam [(F_CKRES-1):0] F_MAXSTEP = F_MIDSTEP + F_HALFSTEP - 1; + + initial assert(F_MINSTEP <= F_MIDSTEP); + initial assert(F_MIDSTEP <= F_MAXSTEP); + + // assume((f_tx_step >= F_MINSTEP)&&(f_tx_step <= F_MAXSTEP)); + // + // + always @(*) assume((f_tx_step == F_MINSTEP) + ||(f_tx_step == F_MIDSTEP) + ||(f_tx_step == F_MAXSTEP)); + + always @(posedge gbl_clk) + f_tx_clock <= f_tx_clock + f_tx_step; + + assign f_txclk = f_tx_clock[F_CKRES-1]; + // + initial f_past_valid_tx = 1'b0; + always @(posedge f_txclk) + f_past_valid_tx <= 1'b1; + + initial assume(i_uart_rx); + + always @(*) + if (i_reset) + assume(i_uart_rx); + + //////////////////////////////////////////////////////////////////////// + // + // The simulated timing generator + + always @(*) + if (i_reset) + assume(!f_tx_busy); + + always @(*) + if (f_tx_busy || i_reset) + assume(!f_tx_start); + + always @(*) + if (i_reset) + assume(f_tx_baud == CLOCKS_PER_BAUD-1); + + initial f_tx_baud = 0; + always @(posedge f_txclk) + if (f_tx_zbaud && (f_tx_busy || f_tx_start)) + f_tx_baud <= CLOCKS_PER_BAUD-1; + else if (!f_tx_zbaud) + f_tx_baud <= f_tx_baud - 1; + + always @(*) + assert(f_tx_baud < CLOCKS_PER_BAUD); + + always @(*) + if (!f_tx_busy) + assert(f_tx_baud == 0); + + assign f_tx_zbaud = (f_tx_baud == 0); + + // But only if we aren't busy + initial assume(f_tx_data == 0); + always @(posedge f_txclk) + if ((!f_tx_zbaud)||(f_tx_busy)||(!f_tx_start)) + assume(f_tx_data == $past(f_tx_data)); + + // Force the data to change on a clock only + always @(posedge gbl_clk) + if ((f_past_valid)&&(!$rose(f_txclk))) + assume($stable(f_tx_data)); + else if (f_tx_busy) + assume($stable(f_tx_data)); + + // + always @(posedge gbl_clk) + if ((!f_past_valid)||(!$rose(f_txclk))) + begin + assume($stable(f_tx_start)); + assume($stable(f_tx_data)); + end + + // + // + // + + // Here's the transmitter itself (roughly) + initial f_tx_busy = 1'b0; + initial f_tx_reg = 0; + always @(posedge f_txclk) + if (!f_tx_zbaud) + begin + assert(f_tx_busy); + end else begin + f_tx_reg <= { 1'b0, f_tx_reg[9:1] }; + if (f_tx_start) + f_tx_reg <= { 1'b1, f_tx_data, 1'b0 }; + end + + // Create a busy flag that we'll use + always @(*) + if (!f_tx_zbaud) + f_tx_busy <= 1'b1; + else if (|f_tx_reg) + f_tx_busy <= 1'b1; + else + f_tx_busy <= 1'b0; + + // + // Tie the TX register to the TX data + always @(posedge f_txclk) + if (f_tx_reg[9]) + begin + assert(f_tx_reg[8:0] == { f_tx_data, 1'b0 }); + end else if (f_tx_reg[8]) + begin + assert(f_tx_reg[7:0] == f_tx_data[7:0] ); + end else if (f_tx_reg[7]) + begin + assert(f_tx_reg[6:0] == f_tx_data[7:1] ); + end else if (f_tx_reg[6]) + begin + assert(f_tx_reg[5:0] == f_tx_data[7:2] ); + end else if (f_tx_reg[5]) + begin + assert(f_tx_reg[4:0] == f_tx_data[7:3] ); + end else if (f_tx_reg[4]) + begin + assert(f_tx_reg[3:0] == f_tx_data[7:4] ); + end else if (f_tx_reg[3]) + begin + assert(f_tx_reg[2:0] == f_tx_data[7:5] ); + end else if (f_tx_reg[2]) + begin + assert(f_tx_reg[1:0] == f_tx_data[7:6] ); + end else if (f_tx_reg[1]) + begin + assert(f_tx_reg[0] == f_tx_data[7]); + end + + // Our counter since we start + initial f_tx_count = 0; + always @(posedge f_txclk) + if (!f_tx_busy) + f_tx_count <= 0; + else + f_tx_count <= f_tx_count + 1'b1; + + always @(*) + if (f_tx_reg == 10'h0) + assume(i_uart_rx); + else + assume(i_uart_rx == f_tx_reg[0]); + + // + // Make sure the absolute transmit clock timer matches our state + // + always @(posedge f_txclk) + if (!f_tx_busy) + begin + if ((!f_past_valid_tx)||(!$past(f_tx_busy))) + assert(f_tx_count == 0); + end else if (f_tx_reg[9]) + begin + assert(f_tx_count == + CLOCKS_PER_BAUD -1 -f_tx_baud); + end else if (f_tx_reg[8]) + begin + assert(f_tx_count == + 2 * CLOCKS_PER_BAUD -1 -f_tx_baud); + end else if (f_tx_reg[7]) + begin + assert(f_tx_count == + 3 * CLOCKS_PER_BAUD -1 -f_tx_baud); + end else if (f_tx_reg[6]) + begin + assert(f_tx_count == + 4 * CLOCKS_PER_BAUD -1 -f_tx_baud); + end else if (f_tx_reg[5]) + begin + assert(f_tx_count == + 5 * CLOCKS_PER_BAUD -1 -f_tx_baud); + end else if (f_tx_reg[4]) + begin + assert(f_tx_count == + 6 * CLOCKS_PER_BAUD -1 -f_tx_baud); + end else if (f_tx_reg[3]) + begin + assert(f_tx_count == + 7 * CLOCKS_PER_BAUD -1 -f_tx_baud); + end else if (f_tx_reg[2]) + begin + assert(f_tx_count == + 8 * CLOCKS_PER_BAUD -1 -f_tx_baud); + end else if (f_tx_reg[1]) + begin + assert(f_tx_count == + 9 * CLOCKS_PER_BAUD -1 -f_tx_baud); + end else if (f_tx_reg[0]) + begin + assert(f_tx_count == + 10 * CLOCKS_PER_BAUD -1 -f_tx_baud); + end else begin + assert(f_tx_count == + 11 * CLOCKS_PER_BAUD -1 -f_tx_baud); + end + + // }}} + //////////////////////////////////////////////////////////////////////// + // + // Receiver + // {{{ + //////////////////////////////////////////////////////////////////////// + // + // + // Count RX clocks since the start of the first stop bit, measured in + // rx clocks + initial f_rx_count = 0; + always @(posedge i_clk) + if (i_reset) + f_rx_count <= 0; + else if (state == RXUL_IDLE) + f_rx_count <= (!ck_uart) ? (chg_counter+2) : 0; + else + f_rx_count <= f_rx_count + 1'b1; + + always @(posedge i_clk) + case(state) + 0: assert(f_rx_count == half_baud + (CLOCKS_PER_BAUD-baud_counter)); + 1: assert(f_rx_count == half_baud + 2 * CLOCKS_PER_BAUD + - baud_counter); + 2: assert(f_rx_count == half_baud + 3 * CLOCKS_PER_BAUD + - baud_counter); + 3: assert(f_rx_count == half_baud + 4 * CLOCKS_PER_BAUD + - baud_counter); + 4: assert(f_rx_count == half_baud + 5 * CLOCKS_PER_BAUD + - baud_counter); + 5: assert(f_rx_count == half_baud + 6 * CLOCKS_PER_BAUD + - baud_counter); + 6: assert(f_rx_count == half_baud + 7 * CLOCKS_PER_BAUD + - baud_counter); + 7: assert(f_rx_count == half_baud + 8 * CLOCKS_PER_BAUD + - baud_counter); + 8: assert((f_rx_count == half_baud + 9 * CLOCKS_PER_BAUD + - baud_counter) + ||(f_rx_count == half_baud + 10 * CLOCKS_PER_BAUD + - baud_counter)); + 9: begin end + 4'hf: begin end + default: + assert(1'b0); + endcase + + always @(*) + assert( ((!zero_baud_counter) + &&(state == RXUL_IDLE) + &&(baud_counter == 0)) + ||((zero_baud_counter)&&(baud_counter == 0)) + ||((!zero_baud_counter)&&(baud_counter != 0))); + + always @(posedge i_clk) + if (!f_past_valid) + assert((state == RXUL_IDLE)&&(baud_counter == 0) + &&(zero_baud_counter)); + + always @(*) + begin + assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h2); + assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h4); + assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h5); + assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h6); + assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h9); + assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'ha); + assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'hb); + assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'hd); + end + + always @(posedge i_clk) + if ((f_past_valid)&&($past(state) >= RXUL_WAIT)&&($past(ck_uart))) + assert(state == RXUL_IDLE); + + always @(posedge i_clk) + if ((f_past_valid)&&($past(state) >= RXUL_WAIT) + &&(($past(state) != RXUL_IDLE)||(state == RXUL_IDLE))) + assert(zero_baud_counter); + + // Calculate an absolute value of the difference between the two baud + // clocks + always @(posedge i_clk) + if (f_past_valid && !$past(i_reset) + && $past(state)==RXUL_IDLE &&(state == RXUL_IDLE)) + begin + assert(($past(ck_uart)) + ||(chg_counter <= + { 1'b0, CLOCKS_PER_BAUD[(TB-1):1] })); + end + + always @(posedge f_txclk) + if (!f_past_valid_tx) + assert((state == RXUL_IDLE)&&(baud_counter == 0) + &&(zero_baud_counter)&&(!f_tx_busy)); + + wire [(TB+3):0] f_tx_count_two_clocks_ago; + assign f_tx_count_two_clocks_ago = f_tx_count - 2; + always @(*) + if (f_tx_count >= f_rx_count + 2) + f_baud_difference = f_tx_count_two_clocks_ago - f_rx_count; + else + f_baud_difference = f_rx_count - f_tx_count_two_clocks_ago; + + localparam F_SYNC_DLY = 8; + + reg [(TB+4+F_CKRES-1):0] f_sub_baud_difference; + reg [F_CKRES-1:0] ck_tx_clock; + reg [((F_SYNC_DLY-1)*F_CKRES)-1:0] q_tx_clock; + reg [TB+3:0] ck_tx_count; + reg [(F_SYNC_DLY-1)*(TB+4)-1:0] q_tx_count; + initial q_tx_count = 0; + initial ck_tx_count = 0; + initial q_tx_clock = 0; + initial ck_tx_clock = 0; + always @(posedge gbl_clk) + if (!f_past_valid || i_reset) + { ck_tx_clock, q_tx_clock } <= 0; + else + { ck_tx_clock, q_tx_clock } <= { q_tx_clock, f_tx_clock }; + always @(posedge gbl_clk) + if (!f_past_valid || i_reset) + { ck_tx_count, q_tx_count } <= 0; + else + { ck_tx_count, q_tx_count } <= { q_tx_count, f_tx_count }; + + + reg [TB+4+F_CKRES-1:0] f_ck_tx_time, f_rx_time; + always @(*) + f_ck_tx_time = { ck_tx_count, !ck_tx_clock[F_CKRES-1], + ck_tx_clock[F_CKRES-2:0] }; + always @(*) + f_rx_time = { f_rx_count, !f_rx_clock[1], f_rx_clock[0], + {(F_CKRES-2){1'b0}} }; + + reg [TB+4+F_CKRES-1:0] f_signed_difference; + always @(*) + f_signed_difference = f_ck_tx_time - f_rx_time; + + always @(*) + if (f_signed_difference[TB+4+F_CKRES-1]) + f_sub_baud_difference = -f_signed_difference; + else + f_sub_baud_difference = f_signed_difference; + + always @(posedge gbl_clk) + if (state == RXUL_WAIT) + assert((!f_tx_busy)||(f_tx_reg[9:1] == 0)); + + always @(posedge gbl_clk) + if (f_past_valid && !$past(i_reset)) + begin + if (state == RXUL_IDLE) + begin + assert((!f_tx_busy)||(f_tx_reg[9])||(f_tx_reg[9:1]==0)); + if (ck_uart) + assert((f_tx_reg[9:1]==0)||(f_tx_count < (3 + CLOCKS_PER_BAUD/2))); + end else if (state == 0) + begin + assert(f_sub_baud_difference + <= 2 * ((CLOCKS_PER_BAUD< 6)) + // assert(i_uart_rx == ck_uart); + + // Make sure the data register matches + always @(posedge i_clk) + case(state) + 4'h0: assert(!data_reg[7]); + 4'h1: assert((data_reg[7] == $past(f_tx_data[0]))&&(!data_reg[6])); + 4'h2: assert(data_reg[7:6] == $past(f_tx_data[1:0])); + 4'h3: assert(data_reg[7:5] == $past(f_tx_data[2:0])); + 4'h4: assert(data_reg[7:4] == $past(f_tx_data[3:0])); + 4'h5: assert(data_reg[7:3] == $past(f_tx_data[4:0])); + 4'h6: assert(data_reg[7:2] == $past(f_tx_data[5:0])); + 4'h7: assert(data_reg[7:1] == $past(f_tx_data[6:0])); + 4'h8: assert(data_reg[7:0] == $past(f_tx_data[7:0])); + endcase + // }}} + //////////////////////////////////////////////////////////////////////// + // + // Cover properties + // {{{ + //////////////////////////////////////////////////////////////////////// + // + always @(posedge i_clk) + cover(o_wr); // Step 626, takes about 20mins + + always @(posedge i_clk) + if (!i_reset && f_past_valid && !$past(i_reset)) + begin + cover(!ck_uart); + cover((f_past_valid)&&($rose(ck_uart))); // 82 + cover((zero_baud_counter)&&(state == RXUL_BIT_ZERO)); // 110 + cover((zero_baud_counter)&&(state == RXUL_BIT_ONE)); // 174 + cover((zero_baud_counter)&&(state == RXUL_BIT_TWO)); // 238 + cover((zero_baud_counter)&&(state == RXUL_BIT_THREE));// 302 + cover((zero_baud_counter)&&(state == RXUL_BIT_FOUR)); // 366 + cover((zero_baud_counter)&&(state == RXUL_BIT_FIVE)); // 430 + cover((zero_baud_counter)&&(state == RXUL_BIT_SIX)); // 494 + cover((zero_baud_counter)&&(state == RXUL_BIT_SEVEN));// 558 + cover((zero_baud_counter)&&(state == RXUL_STOP)); // 622 + cover((zero_baud_counter)&&(state == RXUL_WAIT)); // 626 + end +`endif + // }}} + //////////////////////////////////////////////////////////////////////// + // + // Properties to test via Verilator *and* formal + // {{{ + //////////////////////////////////////////////////////////////////////// + // +`ifdef FORMAL_VERILATOR + // FORMAL properties which can be tested via Verilator as well as + // Yosys FORMAL + always @(*) + assert((state == 4'hf)||(state <= RXUL_WAIT)); + always @(*) + assert(zero_baud_counter == (baud_counter == 0)? 1'b1:1'b0); + always @(*) + assert(baud_counter <= CLOCKS_PER_BAUD-1'b1); + // }}} +`endif +// }}} +endmodule diff --git a/Semaine_4/UART_FIFO/scripts/build.bat b/Semaine_4/UART_FIFO/scripts/build.bat index 5921792..b0c89f6 100644 --- a/Semaine_4/UART_FIFO/scripts/build.bat +++ b/Semaine_4/UART_FIFO/scripts/build.bat @@ -19,7 +19,7 @@ if not exist runs ( ) echo === Étape 1 : Synthèse avec Yosys === -yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx_fifo.v src/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/uart_rx.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" +yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx_fifo.v src/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/rxuartlite.v IP/verilog/uart_rx.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" if errorlevel 1 goto error echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel === diff --git a/Semaine_4/UART_FIFO/scripts/gtkwave.bat b/Semaine_4/UART_FIFO/scripts/gtkwave.bat index 7388f4c..b305019 100644 --- a/Semaine_4/UART_FIFO/scripts/gtkwave.bat +++ b/Semaine_4/UART_FIFO/scripts/gtkwave.bat @@ -1,3 +1,3 @@ @echo off echo === Lancement de GTKWave === -gtkwave runs/uart_rx_fifo.vcd +gtkwave runs/uart_fifo.vcd diff --git a/Semaine_4/UART_FIFO/scripts/simulate.bat b/Semaine_4/UART_FIFO/scripts/simulate.bat index 439cda3..9559a8c 100644 --- a/Semaine_4/UART_FIFO/scripts/simulate.bat +++ b/Semaine_4/UART_FIFO/scripts/simulate.bat @@ -6,7 +6,7 @@ setlocal enabledelayedexpansion set OUT=runs/sim.vvp :: Top-level testbench module -set TOP=tb_uart_rx_fifo +set TOP=tb_uart_fifo :: Répertoires contenant des fichiers .v set DIRS=src/verilog tests/verilog IP/verilog diff --git a/Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v b/Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v index 6a24836..32de85a 100644 --- a/Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v +++ b/Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v @@ -1,25 +1,21 @@ module top_uart_loopback_fifo ( - input wire clk, // 27 MHz - input wire rx, + input wire clk, // 27 MHz + input wire rx, output wire tx, - output reg [5:0] leds + output reg [5:0] leds ); - - // === UART TX === - reg [7:0] wr_data; - reg wr_en; - wire tx_fifo_full; + // UART TX + reg [7:0] wr_data = 0; + reg wr_en = 0; + wire tx_fifo_full; + // UART RX wire [7:0] rd_data; - reg rd_en; - wire data_available; + reg rd_en = 0; + wire data_available; - initial begin - leds = 6'b111111; // Initialiser les LEDs à 0 - end - - // === UART RX === + // RX FIFO Instance uart_rx_fifo uart_rx_inst ( .clk(clk), .rx_pin(rx), @@ -28,7 +24,7 @@ module top_uart_loopback_fifo ( .data_available(data_available) ); - // === UART TX === + // TX FIFO Instance uart_tx_fifo uart_tx_inst ( .clk(clk), .wr_en(wr_en), @@ -37,45 +33,35 @@ module top_uart_loopback_fifo ( .tx_pin(tx) ); - // === FSM pour déclencher la transmission === - localparam IDLE = 0, PREP_READ = 1, READ = 2, WRITE = 3; + // FSM + localparam IDLE = 2'b00, READ = 2'b01, WRITE = 2'b10; reg [1:0] state = IDLE; always @(posedge clk) begin - // Par défaut - wr_en <= 0; - rd_en <= 0; - - // Debug visuel - leds[5] <= rx; - leds[4] <= tx; - leds[3] <= data_available; - leds[2] <= ~fifo_full; + leds <= rd_data[5:0]; case (state) IDLE: begin - if (data_available && !fifo_full) begin - rd_en <= 1; // Mettre rd_en à 1 maintenant - state <= PREP_READ; + rd_en <= 1'b0; + wr_en <= 1'b0; + if (data_available && !tx_fifo_full) begin + rd_en <= 1'b1; + state <= READ; end end - PREP_READ: begin - rd_en <= 1; - state <= READ; - end - READ: begin - rd_en <= 0; + rd_en <= 1'b0; wr_data <= rd_data; + wr_en <= 1'b1; state <= WRITE; end WRITE: begin - wr_en <= 1; + wr_en <= 1'b0; state <= IDLE; end endcase end -endmodule +endmodule \ No newline at end of file diff --git a/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v b/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v index 4d56109..c9e8625 100644 --- a/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v +++ b/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v @@ -1,7 +1,7 @@ module uart_rx_fifo #( parameter CLK_FREQ = 27_000_000, parameter BAUD_RATE = 115200, - parameter FIFO_DEPTH = 8 + parameter FIFO_SIZE = 8 )( input clk, input rd_en, @@ -21,22 +21,18 @@ module uart_rx_fifo #( wire [7:0] fifo_rd_data; // UART Receiver instance - uart_rx #( - .CLK_FREQ(CLK_FREQ), - .BAUD_RATE(BAUD_RATE) - ) uart_rx_inst ( - .clk(clk), - .rst_p(1'b0), - .rx_enable(1'b1), - .rx_pin(rx_pin), - .rx_data(rx_data), - .rx_received(rx_received) - ); + rxuartlite uart_rx_inst ( + .i_clk(clk), + .i_reset(1'b0), + .i_uart_rx(rx_pin), + .o_wr(rx_received), + .o_data(rx_data) + ); // FIFO instance fifo #( .WIDTH(8), - .DEPTH(FIFO_DEPTH) + .SIZE(FIFO_SIZE) ) fifo_inst ( .clk(clk), .wr_en(wr_en), diff --git a/Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v b/Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v index 80ebb84..d09ecc3 100644 --- a/Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v +++ b/Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v @@ -1,7 +1,7 @@ module uart_tx_fifo #( parameter CLK_FREQ = 27_000_000, parameter BAUD_RATE = 115200, - parameter FIFO_DEPTH = 8 + parameter FIFO_SIZE = 8 )( input clk, input wr_en, @@ -32,7 +32,7 @@ module uart_tx_fifo #( // FIFO instantiation fifo #( .WIDTH(8), - .DEPTH(FIFO_DEPTH) + .SIZE(FIFO_SIZE) ) fifo_inst ( .clk(clk), .wr_en(wr_en), diff --git a/Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v b/Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v index 0788abc..1065fd6 100644 --- a/Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v +++ b/Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v @@ -1,49 +1,52 @@ `timescale 1ns/1ps -module tb_uart; +module tb_uart_fifo; reg clk = 0; + reg tx_enable = 0; reg tx_ready; + + wire rx_received; + reg [7:0] data_in = 8'h00; reg [7:0] data_out; - reg rx_received; - wire rx_enable = 1'b1; - - wire pin; + wire rx; + wire tx; always #18.5 clk = ~clk; localparam CLK_FREQ = 27_000_000; localparam BAUD_RATE = 115_200; - uart_rx #( - .CLK_FREQ(CLK_FREQ), - .BAUD_RATE(BAUD_RATE) - ) rx_instance ( - .clk(clk), - .rx_pin(pin), - .rx_data(data_out), - .rx_received(rx_received), - .rx_enable(rx_enable) - ); - - uart_tx #( - .CLK_FREQ(CLK_FREQ), - .BAUD_RATE(BAUD_RATE) - )tx_instance ( + // UART TX Instance + uart_tx emetteur_test ( .clk(clk), .tx_enable(tx_enable), - .tx_ready(tx_ready), .data(data_in), - .tx(pin), - .rst_p(1'b0) + .tx_ready(tx_ready), + .tx(rx) + ); + + // UART RX Instance + rxuartlite recepteur_test ( + .i_clk(clk), + .i_reset(1'b0), + .i_uart_rx(tx), + .o_wr(rx_received), + .o_data(data_out) + ); + + top_uart_loopback_fifo uart ( + .clk(clk), + .rx(rx), + .tx(tx) ); initial begin - $dumpfile("runs/uart.vcd"); - $dumpvars(0, tb_uart); + $dumpfile("runs/uart_fifo.vcd"); + $dumpvars(0, tb_uart_fifo); $display("======== Start UART LOOPBACK test ========="); @@ -57,7 +60,6 @@ module tb_uart; // Attendre wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif - $display("Data received: %d", data_out); // Afficher la valeur recu $display("Data expected: %d", data_in); // Afficher la valeur envoyee #1000; diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/.gitignore b/Semaine_5/UART_ULTRASON_COMMANDS/.gitignore new file mode 100644 index 0000000..33b5bda --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/.gitignore @@ -0,0 +1,4 @@ +runs +.vscode +workspace.code-workspace +*.pyc diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v new file mode 100644 index 0000000..a67914e --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v @@ -0,0 +1,43 @@ + module fifo #( + parameter DEPTH = 16, + parameter WIDTH = 8 +)( + input wire clk, + input wire wr_en, + input wire[WIDTH-1:0] wr_data, + input wire rd_en, + output wire[WIDTH-1:0] rd_data, + + output wire full, + output wire empty +); + + reg [WIDTH-1:0] fifo[0:DEPTH-1]; + reg [3:0] wr_ptr; + reg [3:0] rd_ptr; + reg [3:0] count; + + assign full = (count == DEPTH); + assign empty = (count == 0); + assign rd_data = fifo[rd_ptr]; + + initial begin + wr_ptr = 0; + rd_ptr = 0; + count = 0; + end + + always @(posedge clk) begin + if (wr_en && !full) begin + fifo[wr_ptr] <= wr_data; + wr_ptr <= (wr_ptr + 1) % DEPTH; + count <= count + 1; + end + + if (rd_en && !empty) begin + rd_ptr <= (rd_ptr + 1) % DEPTH; + count <= count - 1; + end + end + +endmodule diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx.v new file mode 100644 index 0000000..9f48d93 --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx.v @@ -0,0 +1,131 @@ +module uart_tx #( + parameter CLK_FREQ = 27_000_000, + parameter BAUD_RATE = 115200 +)( + input wire clk, + input wire rst_p, + input wire[7:0] data, + input wire tx_enable, + + output reg tx_ready, + output wire tx +); + + localparam CYCLE = CLK_FREQ / BAUD_RATE; + + localparam IDLE = 2'd0; + localparam START = 2'd1; + localparam DATA = 2'd2; + localparam STOP = 2'd3; + + reg [1:0] state = IDLE; + reg [1:0] next_state; + reg [15:0] cycle_cnt; //baud counter + reg tx_reg; + reg [2:0] bit_cnt; + reg [7:0] tx_data_latch = 0; + + + assign tx = tx_reg; + + always@(posedge clk or posedge rst_p)begin // Avance d'etat + if(rst_p == 1'b1) + state <= IDLE; + else + state <= next_state; + end + + always@(*) begin + case(state) + IDLE: + if(tx_enable == 1'b1) + next_state = START; + else + next_state = IDLE; + + START: + if(cycle_cnt == CYCLE - 1) + next_state = DATA; + else + next_state = START; + + DATA: + if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) + next_state = STOP; + else + next_state = DATA; + + STOP: + if(cycle_cnt == CYCLE - 1) + next_state = IDLE; + else + next_state = STOP; + default: + next_state = IDLE; + endcase + end + + always@(posedge clk or posedge rst_p)begin // tx_ready block + if(rst_p == 1'b1) + tx_ready <= 1'b0; // Reset + else if(state == IDLE && tx_enable == 1'b1) + tx_ready <= 1'b0; // Pas prêt tant que les données sont valides + else if(state == IDLE) + tx_ready <= 1'b1; + else if(state == STOP && cycle_cnt == CYCLE - 1) + tx_ready <= 1'b1; // Prêt une fois le bit STOP envoyé + else + tx_ready <= tx_ready; // Reste inchangé dans d'autres cas + end + + + + always@(posedge clk or posedge rst_p) begin // tx_data_latch block + if(rst_p == 1'b1) begin + tx_data_latch <= 8'd0; + end else if(state == IDLE && tx_enable == 1'b1) begin + tx_data_latch <= data; // Charger les données de data dans tx_data_latch + end + end + + + always@(posedge clk or posedge rst_p)begin // DATA bit_cnt block + if(rst_p == 1'b1)begin + bit_cnt <= 3'd0; + + end else if(state == DATA) + if(cycle_cnt == CYCLE - 1) + bit_cnt <= bit_cnt + 3'd1; + else + bit_cnt <= bit_cnt; + else + bit_cnt <= 3'd0; + end + + + always@(posedge clk or posedge rst_p)begin // Cycle counter + if(rst_p == 1'b1) + cycle_cnt <= 16'd0; + + else if((state == DATA && cycle_cnt == CYCLE - 1) || next_state != state) + cycle_cnt <= 16'd0; + else + cycle_cnt <= cycle_cnt + 16'd1; + end + + always@(posedge clk or posedge rst_p)begin // tx state managment + if(rst_p == 1'b1) + tx_reg <= 1'b1; + else + case(state) + IDLE,STOP: + tx_reg <= 1'b1; + START: + tx_reg <= 1'b0; + DATA: + tx_reg <= tx_data_latch[bit_cnt]; // SENDING BYTE HERE + default: + tx_reg <= 1'b1; + endcase + end +endmodule diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx_fifo.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx_fifo.v new file mode 100644 index 0000000..80ebb84 --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx_fifo.v @@ -0,0 +1,86 @@ +module uart_tx_fifo #( + parameter CLK_FREQ = 27_000_000, + parameter BAUD_RATE = 115200, + parameter FIFO_DEPTH = 8 +)( + input clk, + input wr_en, + input [7:0] wr_data, + output tx_pin, + output fifo_full +); + + // FIFO wires + wire [7:0] fifo_rd_data; + wire fifo_empty; + reg fifo_rd_en; + + // UART wires + wire tx_ready; + reg uart_tx_enable; + reg [7:0] uart_tx_data; + + // FSM + typedef enum logic [1:0] { + IDLE, + WAIT_READY, + SEND + } state_t; + + state_t state = IDLE; + + // FIFO instantiation + fifo #( + .WIDTH(8), + .DEPTH(FIFO_DEPTH) + ) fifo_inst ( + .clk(clk), + .wr_en(wr_en), + .wr_data(wr_data), + .rd_en(fifo_rd_en), + .rd_data(fifo_rd_data), + .empty(fifo_empty), + .full(fifo_full) + ); + + // UART TX instantiation + uart_tx #( + .CLK_FREQ(CLK_FREQ), + .BAUD_RATE(BAUD_RATE) + ) uart_tx_inst ( + .clk(clk), + .rst_p(1'b0), + .data(uart_tx_data), + .tx_enable(uart_tx_enable), + .tx_ready(tx_ready), + .tx(tx_pin) + ); + + always_ff @(posedge clk) begin + // Valeurs par défaut + fifo_rd_en <= 0; + uart_tx_enable <= 0; + + case (state) + IDLE: begin + if (!fifo_empty) begin + state <= WAIT_READY; + end + end + + WAIT_READY: begin + if (tx_ready) begin + fifo_rd_en <= 1; + state <= SEND; + end + end + + SEND: begin + uart_tx_data <= fifo_rd_data; + uart_tx_enable <= 1; + state <= IDLE; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_fpga.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_fpga.v new file mode 100644 index 0000000..7394173 --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_fpga.v @@ -0,0 +1,151 @@ +module ultrasonic_fpga #( + parameter integer CLK_FREQ = 27_000_000 // Fréquence d'horloge en Hz +)( + input wire clk, + input wire start, + inout wire sig, // Broche bidirectionnelle vers le capteur + output reg [15:0] distance, // Distance mesurée en cm + output reg busy, + output reg done +); + reg [15:0] trig_counter = 0; + reg [31:0] echo_counter = 0; + reg [31:0] echo_div_counter = 0; + reg [15:0] distance_counter = 0; + + reg sig_out; + reg sig_dir; // 1: output, 0: input + + assign sig = sig_dir ? sig_out : 1'bz; // bz pour dire que le fpga laisse le fils libre et n'oblige pas de valeur + + reg sig_int, sig_ok; + + reg [2:0] state = IDLE; + + localparam IDLE = 3'd0, + TRIG_HIGH = 3'd1, + TRIG_LOW = 3'd2, + WAIT_ECHO = 3'd3, + MEASURE_ECHO = 3'd4, + COMPUTE = 3'd5, + DONE = 3'd6, + WAIT_NEXT = 3'd7; + + localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse + localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm + localparam integer MAX_CM = 350; + localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1000000; + + localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms + + reg [31:0] wait_counter; + + always @(posedge clk) begin + sig_int <= sig; + sig_ok <= sig_int; + end + + always @(posedge clk) begin + busy <= (state != IDLE); + end + + always @(posedge clk) begin // FSM + + case (state) + IDLE: begin + done <= 1; + sig_out <= 0; + sig_dir <= 0; + distance <= 0; + if (start) begin + state <= TRIG_HIGH; + trig_counter <= 0; + done <= 0; + end + end + + TRIG_HIGH: begin + sig_out <= 1; + sig_dir <= 1; + if (trig_counter < TRIG_PULSE_CYCLES) begin + trig_counter <= trig_counter + 1; + end else begin + trig_counter <= 0; + state <= TRIG_LOW; + end + end + + TRIG_LOW: begin + sig_out <= 0; + sig_dir <= 0; // Mettre en entrée + + if (sig_ok) begin + state <= TRIG_LOW; + end else + state <= WAIT_ECHO; + end + + WAIT_ECHO: begin + if (sig_ok) begin + echo_counter <= 0; + state <= MEASURE_ECHO; + end else if (echo_counter >= TIMEOUT_CYCLES) begin + distance <= 0; + state <= DONE; + end else begin + echo_counter <= echo_counter + 1; + end + end + + MEASURE_ECHO: begin + if (sig_ok) begin + if (echo_counter < TIMEOUT_CYCLES) begin + echo_counter <= echo_counter + 1; + end else begin + state <= DONE; + end + + end else begin + state <= COMPUTE; + end + end + + COMPUTE: begin + if (echo_counter >= DIST_DIVISOR) begin + echo_counter <= echo_counter - DIST_DIVISOR; + distance_counter <= distance_counter + 1; + state <= COMPUTE; + end else begin + distance <= distance_counter; + state <= DONE; + end + end + + DONE: begin + if (start) begin + wait_counter <= 0; + state <= WAIT_NEXT; + end else begin + state <= IDLE; + end + done <= 1; + end + + WAIT_NEXT: begin + wait_counter <= wait_counter + 1; + if (wait_counter >= WAIT_NEXT_CYCLES) begin + state <= TRIG_HIGH; + trig_counter <= 0; + distance_counter <= 0; + echo_counter <= 0; + end + end + + default: begin + state <= IDLE; // Reset to IDLE state in case of an error + end + endcase + + end + +endmodule \ No newline at end of file diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/README.md b/Semaine_5/UART_ULTRASON_COMMANDS/README.md new file mode 100644 index 0000000..34702e3 --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/README.md @@ -0,0 +1,9 @@ +# ULTRASON VIA UART + +## Description +This project is designed to control an ultrasonic sensor using UART communication. The ultrasonic sensor is used to measure distance, and the data is transmitted via UART to a connected device. + +## Commands +0x01: Start one mesurement of the distance. +0x02: Start continuous mesurement of the distance. +0x03: Stop continuous mesurement of the distance. \ No newline at end of file diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason.cst b/Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason.cst new file mode 100644 index 0000000..507b900 --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason.cst @@ -0,0 +1,9 @@ +IO_LOC "tx" 69; +IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; + +IO_LOC "clk" 4; +IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; + +IO_LOC "sig" 73; +IO_PORT "sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; + diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/project.bat b/Semaine_5/UART_ULTRASON_COMMANDS/project.bat new file mode 100644 index 0000000..6998748 --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/project.bat @@ -0,0 +1,6 @@ +@call c:\oss-cad-suite\environment.bat +@echo off +if "%1"=="sim" call scripts\simulate.bat +if "%1"=="wave" call scripts\gtkwave.bat +if "%1"=="clean" call scripts\clean.bat +if "%1"=="build" call scripts\build.bat diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/scripts/build.bat b/Semaine_5/UART_ULTRASON_COMMANDS/scripts/build.bat new file mode 100644 index 0000000..c4a0fcf --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/scripts/build.bat @@ -0,0 +1,45 @@ +@echo off +setlocal + +rem === Aller à la racine du projet === +cd /d %~dp0\.. + +rem === Config de base === +set DEVICE=GW2AR-LV18QN88C8/I7 +set BOARD=tangnano20k +set TOP=top_uart_ultrason +set CST_FILE=%TOP%.cst +set JSON_FILE=runs/%TOP%.json +set PNR_JSON=runs/pnr_%TOP%.json +set BITSTREAM=runs/%TOP%.fs + +rem === Créer le dossier runs si nécessaire === +if not exist runs ( + mkdir runs +) + +echo === Étape 1 : Synthèse avec Yosys === +yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" +if errorlevel 1 goto error + +echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel === +nextpnr-himbaechel --json %JSON_FILE% --write %PNR_JSON% --device %DEVICE% --vopt cst=constraints/%CST_FILE% --vopt family=GW2A-18C +if errorlevel 1 goto error + +echo === Étape 3 : Packing avec gowin_pack === +gowin_pack -d %DEVICE% -o %BITSTREAM% %PNR_JSON% +if errorlevel 1 goto error + +echo === Étape 4 : Flash avec openFPGALoader === +openFPGALoader -b %BOARD% %BITSTREAM% +if errorlevel 1 goto error + +echo === Compilation et flash réussis === +goto end + +:error +echo === Une erreur est survenue === + +:end +endlocal +pause diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/scripts/clean.bat b/Semaine_5/UART_ULTRASON_COMMANDS/scripts/clean.bat new file mode 100644 index 0000000..6192ae1 --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/scripts/clean.bat @@ -0,0 +1,4 @@ +@echo off +echo === Nettoyage du dossier runs === +rd /s /q runs +mkdir runs diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/scripts/gtkwave.bat b/Semaine_5/UART_ULTRASON_COMMANDS/scripts/gtkwave.bat new file mode 100644 index 0000000..7388f4c --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/scripts/gtkwave.bat @@ -0,0 +1,3 @@ +@echo off +echo === Lancement de GTKWave === +gtkwave runs/uart_rx_fifo.vcd diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/scripts/simulate.bat b/Semaine_5/UART_ULTRASON_COMMANDS/scripts/simulate.bat new file mode 100644 index 0000000..439cda3 --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/scripts/simulate.bat @@ -0,0 +1,29 @@ +@echo off +echo === Simulation avec Icarus Verilog === +setlocal enabledelayedexpansion + +:: Dossier de sortie +set OUT=runs/sim.vvp + +:: Top-level testbench module +set TOP=tb_uart_rx_fifo + +:: Répertoires contenant des fichiers .v +set DIRS=src/verilog tests/verilog IP/verilog + +:: Variable pour stocker les fichiers +set FILES= + +:: Boucle sur chaque dossier +for %%D in (%DIRS%) do ( + for %%F in (%%D\*.v) do ( + set FILES=!FILES! %%F + ) +) + +:: Compilation avec Icarus Verilog +iverilog -g2012 -o %OUT% -s %TOP% %FILES% + +endlocal + +vvp runs/sim.vvp \ No newline at end of file diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason.v b/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason.v new file mode 100644 index 0000000..85a7612 --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason.v @@ -0,0 +1,81 @@ +module top_uart_ultrason ( + input wire clk, // 27 MHz + output wire tx, + inout wire sig, // Capteur ultrason +); + + + // === UART TX WIRE === + reg [7:0] wr_data; + reg wr_en; + wire tx_fifo_full; + + // === UART TX FIFO === + uart_tx_fifo uart_tx_inst ( + .clk(clk), + .wr_en(wr_en), + .wr_data(wr_data), + .fifo_full(tx_fifo_full), + .tx_pin(tx) + ); + + // === Ultrasonic === + reg start = 0; + wire ultrasonic_busy; + wire [15:0] distance; + wire done; + + ultrasonic_fpga #( + .CLK_FREQ(27_000_000) + ) ultrasonic_inst ( + .clk(clk), + .start(start), + .sig(sig), + .distance(distance), + .busy(ultrasonic_busy), + .done(done) + ); + + // === FSM === + localparam IDLE = 0, WAIT = 1 ,SEND_LOW = 2, SEND_HIGH = 3; + reg [1:0] state = IDLE; + + reg [8:0] delay_counter = 0; + + always @(posedge clk) begin + // Activer en continu tant que FIFO pas pleine + start <= 1; + + case (state) + IDLE: begin + wr_en <= 0; + if (done) begin + state <= SEND_LOW; + wr_en <= 1; + end + end + + SEND_LOW: begin + wr_en <= 1; + wr_data <= distance[7:0]; // Octet LSB + state <= SEND_HIGH; + end + + SEND_HIGH: begin + wr_data <= distance[15:8]; // Octet MSB + state <= WAIT; + end + + WAIT: begin // Code non testé + if (delay_counter < 1000000) begin + delay_counter <= delay_counter + 1; + end else begin + state <= IDLE; + delay_counter <= 0; + end + end + + endcase + end + +endmodule diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/uart_ultrason_receiver.py b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/uart_ultrason_receiver.py new file mode 100644 index 0000000..a80d114 --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/uart_ultrason_receiver.py @@ -0,0 +1,21 @@ +import serial + +# === Configuration === +PORT = 'COM7' # Remplace par le port série de ton FPGA (ex: '/dev/ttyUSB0' sur Linux) +BAUDRATE = 115200 # À adapter selon ton uart_tx_fifo +TIMEOUT = 1 # En secondes + +# === Connexion série === +ser = serial.Serial(PORT, BAUDRATE, timeout=TIMEOUT) +print(f"Ouvert sur {PORT} à {BAUDRATE} bauds.") + +try: + while True: + data = ser.read(1) # Lire 1 octet + if data: + value = int.from_bytes(data, byteorder='little') + print(f"Distance mesurée : {value} cm") +except KeyboardInterrupt: + print("\nArrêté par l'utilisateur.") +finally: + ser.close() \ No newline at end of file diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v b/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v new file mode 100644 index 0000000..0788abc --- /dev/null +++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v @@ -0,0 +1,84 @@ +`timescale 1ns/1ps + +module tb_uart; + + reg clk = 0; + reg tx_enable = 0; + reg tx_ready; + reg [7:0] data_in = 8'h00; + reg [7:0] data_out; + + reg rx_received; + wire rx_enable = 1'b1; + + wire pin; + + always #18.5 clk = ~clk; + + localparam CLK_FREQ = 27_000_000; + localparam BAUD_RATE = 115_200; + + uart_rx #( + .CLK_FREQ(CLK_FREQ), + .BAUD_RATE(BAUD_RATE) + ) rx_instance ( + .clk(clk), + .rx_pin(pin), + .rx_data(data_out), + .rx_received(rx_received), + .rx_enable(rx_enable) + ); + + uart_tx #( + .CLK_FREQ(CLK_FREQ), + .BAUD_RATE(BAUD_RATE) + )tx_instance ( + .clk(clk), + .tx_enable(tx_enable), + .tx_ready(tx_ready), + .data(data_in), + .tx(pin), + .rst_p(1'b0) + ); + + initial begin + $dumpfile("runs/uart.vcd"); + $dumpvars(0, tb_uart); + + $display("======== Start UART LOOPBACK test ========="); + + #100; + + data_in <= 8'd234; // 234 + tx_enable <= 1; + wait(tx_ready == 1'b0); + tx_enable <= 0; + + // Attendre + wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif + + $display("Data received: %d", data_out); // Afficher la valeur recu + $display("Data expected: %d", data_in); // Afficher la valeur envoyee + + #1000; + + wait(tx_ready == 1'b1); // Attendre que le signal de reception soit actif + + data_in <= 8'd202; // 202 + tx_enable <= 1; + wait(tx_ready == 1'b0); + tx_enable <= 0; + + // Attendre + wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif + + $display("Data received: %d", data_out); // Afficher la valeur recu + $display("Data expected: %d", data_in); // Afficher la valeur envoyee + + $display("======== END UART TX test ========="); + + #1000; + $stop; + end + +endmodule \ No newline at end of file