diff --git a/Semaine_4/UART/src/verilog/top_uart_loopback.v b/Semaine_4/UART/src/verilog/top_uart_loopback.v
index f71f6c2..a83d995 100644
--- a/Semaine_4/UART/src/verilog/top_uart_loopback.v
+++ b/Semaine_4/UART/src/verilog/top_uart_loopback.v
@@ -41,6 +41,7 @@ module top_uart_loopback (
     reg state = IDLE;
 
     always @(posedge clk) begin
+        leds[5] <= rx;
         case (state)
             IDLE: begin
                 tx_enable <= 0;