From e0a54fb42aea8ea9f25e81f5813c12e0ee900988 Mon Sep 17 00:00:00 2001
From: Gamenight77 <game.night.77176@gmail.com>
Date: Mon, 5 May 2025 14:54:40 +0200
Subject: [PATCH] Add LED indication for RX signal in top_uart_loopback module

---
 Semaine_4/UART/src/verilog/top_uart_loopback.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Semaine_4/UART/src/verilog/top_uart_loopback.v b/Semaine_4/UART/src/verilog/top_uart_loopback.v
index f71f6c2..a83d995 100644
--- a/Semaine_4/UART/src/verilog/top_uart_loopback.v
+++ b/Semaine_4/UART/src/verilog/top_uart_loopback.v
@@ -41,6 +41,7 @@ module top_uart_loopback (
     reg state = IDLE;
 
     always @(posedge clk) begin
+        leds[5] <= rx;
         case (state)
             IDLE: begin
                 tx_enable <= 0;