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Bloquer a cause du tx

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Gamenight77
2025-05-13 12:22:50 +02:00
parent d1f907f7b6
commit e124c7c0c4
9 changed files with 523 additions and 37 deletions
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35
Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v
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@@ -16,7 +16,7 @@ module uart_tx_fifo #(
reg fifo_rd_en;
// UART wires
wire tx_ready;
wire tx_busy;
reg uart_tx_enable;
reg [7:0] uart_tx_data;
@@ -24,6 +24,7 @@ module uart_tx_fifo #(
typedef enum logic [1:0] {
IDLE,
WAIT_READY,
READ_FIFO,
SEND
} state_t;
@@ -44,39 +45,39 @@ module uart_tx_fifo #(
);
// UART TX instantiation
uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) uart_tx_inst (
.clk(clk),
.rst_p(1'b0),
.data(uart_tx_data),
.tx_enable(uart_tx_enable),
.tx_ready(tx_ready),
.tx(tx_pin)
txuartlite uart_tx_inst (
.i_clk(clk),
.i_reset(1'b0),
.i_wr(uart_tx_enable),
.i_data(uart_tx_data),
.o_uart_tx(tx_pin),
.o_busy(tx_busy)
);
always_ff @(posedge clk) begin
// Valeurs par défaut
fifo_rd_en <= 0;
uart_tx_enable <= 0;
case (state)
IDLE: begin
if (!fifo_empty) begin
if (!fifo_empty)
state <= WAIT_READY;
end
end
WAIT_READY: begin
if (tx_ready) begin
if (!tx_busy) begin
fifo_rd_en <= 1;
state <= SEND;
state <= READ_FIFO;
end
end
READ_FIFO: begin
// fifo_rd_data sera valide ici
uart_tx_data <= fifo_rd_data;
state <= SEND;
end
SEND: begin
uart_tx_data <= fifo_rd_data;
uart_tx_enable <= 1;
state <= IDLE;
end