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forked from tanchou/Verilog

Bloquer a cause du tx

This commit is contained in:
Gamenight77
2025-05-13 12:22:50 +02:00
parent d1f907f7b6
commit e124c7c0c4
9 changed files with 523 additions and 37 deletions

View File

@@ -30,7 +30,7 @@ module tb_uart_rx_fifo;
uart_rx_fifo #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE),
.FIFO_DEPTH(8)
.FIFO_SIZE(8)
) rx_fifo_instance (
.clk(clk),
.rx_pin(rx),

View File

@@ -14,19 +14,22 @@ module tb_uart_tx_fifo;
always #18.5 clk = ~clk;
other_uart_rx rx_instance(
.clk(clk),
.rx_pin(tx), // tx is connected to rx for testing
.rst_n(1'b1),
.rx_data(data_out),
.rx_data_valid(rx_recieved),
.rx_data_ready(1'b1)
// UART RX wires
wire [7:0] rx_data;
wire rx_received;
rxuartlite uart_rx_inst (
.i_clk(clk),
.i_reset(1'b0),
.i_uart_rx(tx),
.o_wr(rx_received),
.o_data(rx_data)
);
uart_tx_fifo #(
.CLK_FREQ(27_000_000),
.BAUD_RATE(115_200),
.FIFO_DEPTH(8)
.FIFO_SIZE(8)
)tx_fifo_instance (
.clk(clk),
.wr_en(wr_en),
@@ -43,21 +46,23 @@ module tb_uart_tx_fifo;
#50;
data_in <= 8'd234;
data_in <= 8'h23;
wr_en <= 1'b1; // Activer l'écriture dans la FIFO
#37;
wr_en <= 1'b0; // Désactiver l'écriture dans la FIFO
data_in <= 8'd123;
/**/data_in <= 8'h75;
wr_en <= 1'b1; // Activer l'écriture dans la FIFO
#37;
wr_en <= 1'b0; // Désactiver l'écriture dans la FIFO
data_in <= 8'd45;
data_in <= 8'hff;
wr_en <= 1'b1; // Activer l'écriture dans la FIFO
#37;
wr_en <= 1'b0; // Désactiver l'écriture dans la FIFO
#5000
$display("======== END UART TX FIFO test =========");
#1000000;