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Bloquer a cause du tx

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Gamenight77
2025-05-13 12:22:50 +02:00
parent d1f907f7b6
commit e124c7c0c4
9 changed files with 523 additions and 37 deletions
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17
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx_fifo.v
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@@ -24,6 +24,7 @@ module uart_tx_fifo #(
typedef enum logic [1:0] {
IDLE,
WAIT_READY,
READ_FIFO,
SEND
} state_t;
@@ -57,13 +58,14 @@ module uart_tx_fifo #(
);
always_ff @(posedge clk) begin
// Valeurs par défaut
fifo_rd_en <= 0;
uart_tx_enable <= 0;
case (state)
IDLE: begin
fifo_rd_en <= 0;
uart_tx_enable <= 0;
if (!fifo_empty) begin
fifo_rd_en <= 1;
state <= WAIT_READY;
end
end
@@ -71,12 +73,17 @@ module uart_tx_fifo #(
WAIT_READY: begin
if (tx_ready) begin
fifo_rd_en <= 1;
state <= SEND;
state <= READ_FIFO;
end
end
READ_FIFO: begin
uart_tx_data <= fifo_rd_data;
state <= SEND;
fifo_rd_en <= 0;
end
SEND: begin
uart_tx_data <= fifo_rd_data;
uart_tx_enable <= 1;
state <= IDLE;
end