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Gamenight77
2025-05-16 10:34:32 +02:00
parent 861c9869f5
commit e66a464812
7 changed files with 615 additions and 144 deletions
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25
Semaine_4/FIFO/src/verilog/fifo.v
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@@ -12,10 +12,12 @@
output wire empty
);
localparam LOGSIZE = $clog2(SIZE);
reg [WIDTH-1:0] fifo[0:SIZE-1];
reg [3:0] wr_ptr;
reg [3:0] rd_ptr;
reg [3:0] count;
reg [LOGSIZE-1:0] wr_ptr;
reg [LOGSIZE-1:0] rd_ptr;
reg [LOGSIZE:0] count;
assign full = (count == SIZE);
assign empty = (count == 0);
@@ -27,17 +29,20 @@
end
always @(posedge clk) begin // IN
if (wr_en && !full) begin
rd_data <= fifo[rd_ptr];
if (wr_en && !full && rd_en && !empty) begin
fifo[wr_ptr] <= wr_data;
wr_ptr <= (wr_ptr + 1) % SIZE;
wr_ptr <= (wr_ptr == SIZE - 1) ? 0 : (wr_ptr + 1) ;
rd_ptr <= (rd_ptr == SIZE - 1) ? 0 : (rd_ptr + 1) ;
end else if (wr_en && !full) begin
fifo[wr_ptr] <= wr_data;
wr_ptr <= (wr_ptr == SIZE - 1) ? 0 : (wr_ptr + 1) ;
count <= count + 1;
end
if (rd_en && !empty) begin // OUT
rd_data <= fifo[rd_ptr];
rd_ptr <= (rd_ptr + 1) % SIZE;
end else if (rd_en && !empty) begin // OUT
rd_ptr <= (rd_ptr == SIZE - 1) ? 0 : (rd_ptr + 1) ;
count <= count - 1;
end
end
endmodule

6
Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v
View File

@@ -67,19 +67,21 @@ module uart_tx_fifo #(
WAIT_READY: begin
if (!tx_busy) begin
fifo_rd_en <= 1;
uart_tx_data <= fifo_rd_data;
state <= READ_FIFO;
end
end
READ_FIFO: begin
// fifo_rd_data sera valide ici
uart_tx_data <= fifo_rd_data;
fifo_rd_en <= 0;
uart_tx_enable <= 1;
state <= SEND;
end
SEND: begin
uart_tx_enable <= 1;
state <= IDLE;
uart_tx_enable <= 0;
end
endcase
end