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Sa a l'air de fonctionner

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Gamenight77
2025-05-16 10:34:32 +02:00
parent 861c9869f5
commit e66a464812
7 changed files with 615 additions and 144 deletions
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6
Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v
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@@ -67,19 +67,21 @@ module uart_tx_fifo #(
WAIT_READY: begin
if (!tx_busy) begin
fifo_rd_en <= 1;
uart_tx_data <= fifo_rd_data;
state <= READ_FIFO;
end
end
READ_FIFO: begin
// fifo_rd_data sera valide ici
uart_tx_data <= fifo_rd_data;
fifo_rd_en <= 0;
uart_tx_enable <= 1;
state <= SEND;
end
SEND: begin
uart_tx_enable <= 1;
state <= IDLE;
uart_tx_enable <= 0;
end
endcase
end