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Gamenight77
2025-05-16 10:34:32 +02:00
parent 861c9869f5
commit e66a464812
7 changed files with 615 additions and 144 deletions
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187
Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
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@@ -38,7 +38,7 @@ module top_uart_ultrason_command (
reg start = 0;
wire ultrasonic_busy;
wire [15:0] distance;
wire done;
wire ultrason_done;
ultrasonic_fpga #(
.CLK_FREQ(27_000_000)
@@ -48,139 +48,130 @@ module top_uart_ultrason_command (
.sig(ultrason_sig),
.distance(distance),
.busy(ultrasonic_busy),
.done(done)
.done(ultrason_done)
);
// === FSM ===
localparam IDLE = 0, READ = 1, DECODE = 2;
localparam STOP = 3, ONE = 1, CONTINUOUS = 2;
localparam IDLE = 0, ONESTART = 1, ONESTOP = 2, CONTINUOUSSTART = 3, CONTINUOUSSTOP = 4, WAIT = 5, NEXT_FIFO = 6;
reg [1:0] rx_state = IDLE;
reg [1:0] command = 0;
reg [8:0] delay_counter = 0;
reg [31:0] delay_counter = 0;
localparam MESURE = 1, SEND_LOW = 2, SEND_HIGH = 3, WAIT = 4;
reg [1:0] tx_state = MESURE;
reg [1:0] mesure = STOP;
localparam US_STATE_WIDTH = $clog2(NEXT_FIFO)+1;
reg [US_STATE_WIDTH-1:0] mesure_state = IDLE;
always @(posedge clk) begin
leds [4] <= data_available;
if (data_available) begin
command <= rd_data[1:0];
leds <= rd_data[7:2];
end
end
case (rx_state)
always @(posedge clk) begin // Mesure state machine
case (mesure_state)
IDLE: begin
leds [5] <= 0;
wr_en <= 0;
rd_en <= 0;
if (data_available && !tx_fifo_full) begin
rd_en <= 1'b1;
rx_state <= READ;
if (command == 2'd1 && data_available) begin
mesure_state <= ONESTART;
rd_en <= 1;
end else if (command == 2'd2 && data_available) begin
mesure_state <= CONTINUOUSSTART;
rd_en <= 1;
end else begin
rx_state <= IDLE;
mesure_state <= IDLE;
rd_en <= 0;
end
end
READ: begin
leds [5] <= 1;
rd_en <= 1'b1;
rx_state <= DECODE;
ONESTART: begin
start <= 1;
mesure_state <= ONESTOP;
rd_en <= 0;
end
DECODE: begin
case (rd_data)
8'h01: begin // Start mesure one mesure
start <= 1;
mesure <= ONE;
rx_state <= IDLE;
end
ONESTOP: begin
start <= 0;
mesure_state <= IDLE;
end
8'h02: begin // Start mesure continuous mesure
start <= 1;
mesure <= CONTINUOUS;
rx_state <= IDLE;
end
CONTINUOUSSTART: begin
if (command == 3) begin
mesure_state <= NEXT_FIFO;
rd_en <= 1;
end else begin
mesure_state <= CONTINUOUSSTOP;
start <= 1;
rd_en <= 0;
end
end
8'h03: begin // Stop mesure
start <= 0;
mesure <= STOP;
rx_state <= IDLE;
end
CONTINUOUSSTOP: begin
start <= 0;
mesure_state <= WAIT;
end
default: begin
mesure <= STOP;
rx_state <= IDLE;
end
endcase
WAIT: begin // Compteur 0.5s
if (delay_counter > 1) begin
delay_counter <= delay_counter - 1;
end else begin
mesure_state <= CONTINUOUSSTART;
delay_counter <= 13500000;
end
end
NEXT_FIFO: begin
rd_en <= 1;
mesure_state <= IDLE;
end
endcase
end
// Mesure block
always @(posedge clk) begin
leds <= mesure[1:0];
localparam BUSY = 1, SEND_LOW = 2, SEND_HIGH = 3, DONE = 4;
reg [1:0] saver_state = IDLE;
always @(posedge clk) begin // FSM Pour enregistrer la distance
case (saver_state)
IDLE: begin
wr_en <= 0;
if (ultrasonic_busy) begin
saver_state <= BUSY;
end else begin
saver_state <= IDLE;
end
end
case (tx_state)
MESURE: begin
case (mesure)
STOP: begin // Stop mesure
start <= 0;
end
ONE: begin // One mesure
start <= 1;
if (done) begin
tx_state <= SEND_LOW;
wr_en <= 1;
mesure <= STOP;
end else begin
tx_state <= MESURE;
mesure <= ONE;
end
end
CONTINUOUS: begin // Continuous mesure
start <= 1;
if (done) begin
tx_state <= SEND_LOW;
wr_en <= 1;
end else begin
tx_state <= IDLE;
end
end
default:
start <= 0;
endcase
end
BUSY: begin
if (ultrason_done) begin
saver_state <= SEND_LOW;
wr_en <= 1;
wr_data <= distance[7:0];
end else if(ultrasonic_busy) begin
saver_state <= BUSY;
end else begin
saver_state <= IDLE;
end
end
SEND_LOW: begin
wr_en <= 1;
wr_data <= distance[7:0]; // Octet LSB
tx_state <= WAIT;
wr_data <= distance[15:8];
saver_state <= SEND_HIGH;
end
SEND_HIGH: begin
wr_data <= distance[15:8]; // Octet MSB
tx_state <= WAIT;
end
WAIT: begin // Code non testé
if (delay_counter < 1000000) begin
delay_counter <= delay_counter + 1;
end else begin
tx_state <= MESURE;
delay_counter <= 0;
end
wr_en <= 0;
saver_state <= DONE;
end
DONE: begin
wr_data <= 0;
wr_en <= 0;
saver_state <= IDLE;
end
default:
tx_state <= MESURE;
endcase
end
endmodule