From ebe6cefda47426f6f61289f1e084e499a7849c62 Mon Sep 17 00:00:00 2001 From: Tanchou Date: Thu, 5 Jun 2025 15:59:12 +0200 Subject: [PATCH] Update S4 Uart FIFO --- Semaine_4/UART_FIFO/IP/verilog/fifo.v | 25 +++++++++++-------- .../UART_FIFO/src/verilog/uart_rx_fifo.v | 9 ++++++- .../UART_FIFO/src/verilog/uart_tx_fifo.v | 7 +++++- 3 files changed, 29 insertions(+), 12 deletions(-) diff --git a/Semaine_4/UART_FIFO/IP/verilog/fifo.v b/Semaine_4/UART_FIFO/IP/verilog/fifo.v index 6135d3b..82915e2 100644 --- a/Semaine_4/UART_FIFO/IP/verilog/fifo.v +++ b/Semaine_4/UART_FIFO/IP/verilog/fifo.v @@ -12,10 +12,12 @@ output wire empty ); + localparam LOGSIZE = $clog2(SIZE); + reg [WIDTH-1:0] fifo[0:SIZE-1]; - reg [3:0] wr_ptr; - reg [3:0] rd_ptr; - reg [3:0] count; + reg [LOGSIZE-1:0] wr_ptr; + reg [LOGSIZE-1:0] rd_ptr; + reg [LOGSIZE:0] count; assign full = (count == SIZE); assign empty = (count == 0); @@ -27,17 +29,20 @@ end always @(posedge clk) begin // IN - if (wr_en && !full) begin + rd_data <= fifo[rd_ptr]; + if (wr_en && !full && rd_en && !empty) begin fifo[wr_ptr] <= wr_data; - wr_ptr <= (wr_ptr + 1) % SIZE; + wr_ptr <= (wr_ptr == SIZE - 1) ? 0 : (wr_ptr + 1) ; + rd_ptr <= (rd_ptr == SIZE - 1) ? 0 : (rd_ptr + 1) ; + end else if (wr_en && !full) begin + fifo[wr_ptr] <= wr_data; + wr_ptr <= (wr_ptr == SIZE - 1) ? 0 : (wr_ptr + 1) ; count <= count + 1; - end - - if (rd_en && !empty) begin // OUT - rd_data <= fifo[rd_ptr]; - rd_ptr <= (rd_ptr + 1) % SIZE; + end else if (rd_en && !empty) begin // OUT + rd_ptr <= (rd_ptr == SIZE - 1) ? 0 : (rd_ptr + 1) ; count <= count - 1; end + end endmodule diff --git a/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v b/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v index d521fde..f44a949 100644 --- a/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v +++ b/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v @@ -19,8 +19,15 @@ module uart_rx_fifo #( wire fifo_empty; wire fifo_full; + localparam integer CPB = CLK_FREQ/BAUD_RATE; + // UART Receiver instance - rxuartlite uart_rx_inst ( + rxuartlite + #( + .CLOCKS_PER_BAUD(CPB), + .TIMER_BITS($clog2(CPB)+1) + ) uart_rx_inst + ( .i_clk(clk), .i_reset(1'b0), .i_uart_rx(rx_pin), diff --git a/Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v b/Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v index 5d5387b..94fdb01 100644 --- a/Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v +++ b/Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v @@ -45,7 +45,12 @@ module uart_tx_fifo #( ); // UART TX instantiation - txuartlite uart_tx_inst ( + txuartlite + #( + .CLOCKS_PER_BAUD(CLK_FREQ/BAUD_RATE), + .TIMING_BITS($clog2(CLK_FREQ/BAUD_RATE)+1) + ) uart_tx_inst + ( .i_clk(clk), .i_reset(1'b0), .i_wr(uart_tx_enable),