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forked from tanchou/Verilog

Implement UART and ultrasonic sensor integration with FIFO for data transmission

This commit is contained in:
Gamenight77
2025-05-07 10:27:17 +02:00
parent abef18227c
commit ec1c69cf8f
14 changed files with 685 additions and 0 deletions

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IO_LOC "tx" 69;
IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "clk" 4;
IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "sig" 73;
IO_PORT "sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;