Implement UART and ultrasonic sensor integration with FIFO for data transmission

Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v

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+module top_uart_ultrason (
+    input wire clk, // 27 MHz
+    output wire tx,
+    inout wire sig, // Capteur ultrason
+);
+
+
+    // === UART TX WIRE ===
+    reg [7:0] wr_data;
+    reg wr_en;
+    wire tx_fifo_full;
+    
+    // === UART TX FIFO ===
+    uart_tx_fifo uart_tx_inst (
+        .clk(clk),
+        .wr_en(wr_en),
+        .wr_data(wr_data),
+        .fifo_full(tx_fifo_full),
+        .tx_pin(tx)
+    );
+
+    // === Ultrasonic ===
+    reg start = 0;
+    wire ultrasonic_busy;
+    wire [15:0] distance;
+    wire done;
+
+    ultrasonic_fpga #(
+        .CLK_FREQ(27_000_000)
+    ) ultrasonic_inst (
+        .clk(clk),
+        .start(start),
+        .sig(sig),
+        .distance(distance),
+        .busy(ultrasonic_busy),
+        .done(done)
+    );
+
+    // === FSM ===
+    localparam IDLE = 0, SEND_LOW = 2, SEND_HIGH = 3;
+    reg [1:0] state = IDLE;
+
+    always @(posedge clk) begin
+        // Activer en continu tant que FIFO pas pleine
+        start <= 1;
+
+        case (state)
+            IDLE: begin
+                wr_en <= 0;
+                if (done) begin
+                    state <= SEND_LOW;
+                    wr_en <= 1;
+                end
+            end
+
+            SEND_LOW: begin
+                wr_en <= 1;
+                wr_data <= distance[7:0]; // Octet LSB
+                state <= IDLE;
+            end
+
+            SEND_HIGH: begin
+                wr_data <= distance[15:8]; // Octet MSB
+                state <= IDLE;
+            end
+
+        endcase
+    end
+
+endmodule