diff --git a/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/tb_ultrasonic_fpga.v b/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/tb_ultrasonic_fpga.v
index 290f24a..33523d2 100644
--- a/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/tb_ultrasonic_fpga.v
+++ b/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/tb_ultrasonic_fpga.v
@@ -37,26 +37,7 @@ module tb_ultrasonic_fpga;
         #40;
         start = 0;
 
-        wait (trig_out == 1);
-        t_start = $time;
-
-        // Attendre qu'il redescende
-        wait (trig_out == 0);
-        t_end = $time;
-
-        $display("Trig HIGH duration: %0dns", t_end - t_start);
-
-        if ((t_end - t_start) >= 9500 && (t_end - t_start) <= 10500) begin
-            $display("Trigger signal is high for 10us.");
-
-            #10;
-            echo = 1;
-
-            #5800;// Echo dure 5800ns (≈ 100 cycles @ 27MHz => ≈ 100 cm aller-retour)
-            echo = 0;
-        end else begin
-            $display("Trigger signal is NOT high for 10us.");
-        end
+ 
 
         #500;
 
diff --git a/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_sensor.v b/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_sensor.v
new file mode 100644
index 0000000..201886e
--- /dev/null
+++ b/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_sensor.v
@@ -0,0 +1,79 @@
+module ultrasonic_sensor(// Simulation of an ultrasonic sensor
+    input wire clk,               
+    inout wire signal,            // Signal from the ultrasonic sensor
+);
+    reg [2:0] state, next_state;
+    reg sig_dir;             // 1: output, 0: input
+    reg [15:0] trig_counter;               // Counter for the trigger pulse
+    reg [31:0] echo_counter;               // Echo signal
+    reg valid_trig;                  // Valid trigger signal
+
+    reg echo_sended; // Flag to indicate if echo has been sent
+
+    localparam  S_WAIT_TRIG       = 3'd0,
+                S_MEASURE_TRIG    = 3'd1,
+                S_SEND_ECHO       = 3'd2,
+
+    localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
+
+    always @(*) begin
+        case (state)
+            S_WAIT_TRIG: begin
+                sig_dir = 0; 
+                if (signal == 1) begin
+                    next_state = S_MEASURE_TRIG;
+                end else begin
+                    next_state = S_WAIT_TRIG;
+                end
+            end
+
+            S_MEASURE_TRIG: begin
+                sig_dir = 0; 
+                if (valid_trig)begin
+                    next_state = S_SEND_ECHO;
+                end
+            end
+
+            S_SEND_ECHO: begin
+                sig_dir = 1; // Mettre en sortie
+
+                if (echo_sended) begin
+                    echo_sended = 0; // Reset flag
+                    next_state = S_WAIT_TRIG;
+                end else begin
+                    signal = 1; // Send echo signal
+                    #5800; // Wait for 5800ns (≈ 100 cycles @ 27MHz => ≈ 100 cm aller-retour)
+                    signal = 0; // Stop sending echo signal
+                    echo_sended = 1; // Set flag to indicate echo has been sent
+                end
+                next_state = S_WAIT_TRIG;
+            end
+
+            default: begin
+                sig_dir = 0; 
+                next_state = S_WAIT_TRIG;
+            end
+        endcase
+    end
+
+    always @(posedge clk) begin
+        state <= next_state;
+        if (~sig_dir) begin
+            signal <= 1'bz; 
+        end
+    end
+
+    always @(posedge clk) begin
+        if (state == S_MEASURE_TRIG) begin
+            if (signal == 1) begin
+                trig_counter <= trig_counter + 1;
+            end else begin
+                if (trig_counter >= TRIG_PULSE_CYCLES-2 && trig_counter <= TRIG_PULSE_CYCLES+2) begin
+                    valid_trig <= 1;
+                end else begin
+                    valid_trig <= 0;
+                end
+            end
+        end 
+    end
+endmodule
\ No newline at end of file