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Help/presentation_examples/blink/tests/cocotb/counter_test.py

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+import cocotb
+from cocotb.triggers import Timer, RisingEdge, First
+
+# from cocotb.triggers import FallingEdge, RisingEdge, First, Timer, Event
+
+from cocotb_test.simulator import run
+import pytest
+import os
+
+async def generate_clock(dut):
+    """Generate clock pulses."""
+
+    # for cycle in range(100):
+    while True:
+        dut.clk.value = 0
+        await Timer(5, "ns")
+        dut.clk.value = 1
+        await Timer(5, "ns")
+
+
+
+
+
+@cocotb.test()
+async def counter_simple_test(dut):
+    await cocotb.start(generate_clock(dut))  # run the clock "in the background"
+
+    
+    #dut._log.info("my_signal_1 is %s", dut.my_signal_1.value)
+    
+    # await Timer(10000, units='ns')
+
+    #for i in range(dut.WRITE_NB.value):
+    #    await RisingEdge(dut.write_transaction)
+    #for i in range(dut.READ_NB.value):
+    #    await RisingEdge(dut.read_transaction)
+    #await Timer(400, units="ns")
+
+    await RisingEdge(dut.clk)
+    dut.reset.value = 1
+    await RisingEdge(dut.clk)
+    dut.reset.value = 0
+    dut.en.value = 1
+
+    await Timer(400, units="ns")
+    await RisingEdge(dut.clk)
+    dut.en.value = 0
+    await Timer(50, units="ns")
+    await RisingEdge(dut.clk)
+    dut.en.value = 1
+    await Timer(500, units="ns")
+
+    # assert strobe : have a new process counting strobes
+
+
+
+def test_counter_runner():
+    current_dir = os.path.dirname(__file__)
+    root = "{current_dir}../.."
+    print(f"root: {root}")
+    run(
+        # python_search=[os.path.join(current_dir, "../cocotb/")],
+        python_search=[current_dir],
+        verilog_sources=[
+            f"{root}/src/verilog/counter.v",
+        ],  # sources
+        toplevel="counter",  # top level HDL
+        module="counter_test",  # name of cocotb test module
+        sim_build=f"{root}/runs/cocotb",  # + "_".join(("{}={}".format(*i) for i in parameters.items())),
+        #       parameters = parameters,
+        waves=1,
+    )
+
+@pytest.mark.skipif(os.getenv("SIM") == "verilator", reason="Custom for verilator")
+@pytest.mark.parametrize("parameters", [{"WIDTH": 4, "INITIAL_VALUE": 5}, {"WIDTH": 8, "INITIAL_VALUE": 15}, {"WIDTH": 8, "INITIAL_VALUE": 255}])
+def test_parametrized_counter_runner(parameters):
+    current_dir = os.path.dirname(__file__)
+    #from pathlib import Path
+    #proj_path = Path(__file__).resolve().parent
+    root = "{current_dir}../.."
+    run(
+        # python_search=[os.path.join(current_dir, "../cocotb/")],
+        python_search=[current_dir],
+        verilog_sources=[
+            f"{root}/src/verilog/counter.v",
+        ],  # sources
+        toplevel="counter",  # top level HDL
+        module="counter_test",  # name of cocotb test module
+        sim_build=f"{root}/runs/cocotb/" + "_".join(("{}={}".format(*i) for i in parameters.items())),
+        parameters = parameters,
+        waves=1,
+    )
+
+
+if __name__ == "__main__":
+    test_counter_runner()