verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

struct

Browse Source
This commit is contained in:
Gamenight77
2025-05-02 15:51:18 +02:00
parent 0faab53c30
commit f5e73d7379
105 changed files with 707398 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
Help/presentation_examples/blink_vivado/constraints/blink_led.cst Normal file
View File

@@ -0,0 +1,4 @@
IO_LOC "led" 15;
IO_PORT "led" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clk" 4;
IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8;