forked from tanchou/Verilog
struct
This commit is contained in:
4
Help/presentation_examples/example1/.gitignore
vendored
Normal file
4
Help/presentation_examples/example1/.gitignore
vendored
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@@ -0,0 +1,4 @@
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runs
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.vscode
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workspace.code-workspace
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*.pyc
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2
Help/presentation_examples/example1/project.bat
Normal file
2
Help/presentation_examples/example1/project.bat
Normal file
@@ -0,0 +1,2 @@
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@call c:\tools\oss-cad-suite\environment.bat
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@tclsh scripts\project.tcl %*
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@@ -0,0 +1,20 @@
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puts "Starting TCL script"
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#set path test1b_tb
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#gtkwave::forceOpenTreeNode $path
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set nfacs [ gtkwave::getNumFacs ]
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puts "There are $nfacs signals"
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set l [list]
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for {set i 0} {$i < $nfacs } {incr i} {
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set facname [ gtkwave::getFacName $i ]
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set numdots [ expr {[llength [split $facname .]] - 1}]
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# puts "$numdots"
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if {$numdots == 1} {
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lappend l "$facname"
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puts "Added signal $facname"
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}
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}
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set num_added [ gtkwave::addSignalsFromList $l ]
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gtkwave::setZoomRangeTimes [ gtkwave::getMinTime ] [ gtkwave::getMaxTime ]
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puts "Start time [ gtkwave::getMinTime ] end time: [ gtkwave::getMaxTime ]"
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176
Help/presentation_examples/example1/scripts/project.tcl
Normal file
176
Help/presentation_examples/example1/scripts/project.tcl
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@@ -0,0 +1,176 @@
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# Tcl launcher script for the project
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namespace eval project_launcher {
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# Help information for this script
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proc print_help {} {
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variable script_file "project.tcl"
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puts "\nDescription:"
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puts "Perform actions related to this project.\n"
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puts "Syntax:"
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puts "$script_file"
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puts "$script_file \[action\] \[args\]"
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puts "Usage:"
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puts "Name Description"
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puts "-------------------------------------------------------------------------"
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puts "\[action\] Determine the action to be performed. Default value: help\n"
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puts " Current actions: help, clean, sim, verify, test, view\n"
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puts "\[args\] Arguments related to the action.\n"
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puts " --root <dir> changes the root reference for the project.\n"
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puts "-------------------------------------------------------------------------\n"
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exit 0
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}
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proc do_clean { root_dir } {
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variable dir "$root_dir/runs"
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puts "Cleaning all files in directory $dir...\n"
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# Checking if the folder is empty to avoid error
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if {[catch { glob "$dir/*" } result] != 1} {
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file delete -force -- {*}[glob "$dir/*" ]
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}
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}
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proc do_sim_icarus { root_dir verbose } {
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# Checking if the folder is empty to avoid error
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if {[file exists "$root_dir/scripts/run_iverilog.tcl"] == 1} {
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#global root_dir_loc $root_dir
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#source $root_dir/scripts/run_iverilog.tcl
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try {
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set results [exec tclsh $root_dir/scripts/run_iverilog.tcl $root_dir ]
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set status 0
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} trap CHILDSTATUS {results options} {
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set status [lindex [dict get $options -errorcode] 2]
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}
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if {$status != 0} {
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puts "Problem running the script :"
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puts $results
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return
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}
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if {[expr $verbose]} {
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# output the result of the execution
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puts $results
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}
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} else {
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puts "The script run_iverilog.tcl does not exist in $root_dir/scripts"
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}
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}
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proc do_sim_pytest { root_dir verbose } {
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exec pytest $root_dir/tests/ >@stdout 2>@stderr
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}
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proc do_formal { root_dir } {
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# We suppose that the sby file is meant to be run from the inside of the folder
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# hence we cd there
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if {[file pathtype $root_dir] != "absolute"} {
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set root_dir "../$root_dir"
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}
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#set root_dir [file normalize $root_dir]
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cd verification
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#variable fname [glob -nocomplain $root_dir/verification/*.sby]
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variable fname [glob -nocomplain *.sby]
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if {[llength $fname]} {
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set fname [lindex $fname 0]
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puts "Using $fname file..."
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exec sby -f $fname --prefix $root_dir/runs/verification/counter >@stdout 2>@stderr
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} else {
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puts "There are no .sby files present..."
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cd ..
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return
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}
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cd ..
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}
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proc do_view { root_dir } {
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# Checking if the folder is empty to avoid error
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if {[file exists "$root_dir/scripts/run_gtkwave.tcl"] == 1} {
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try {
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set results [exec tclsh $root_dir/scripts/run_gtkwave.tcl $root_dir ]
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set status 0
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} trap CHILDSTATUS {results options} {
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set status [lindex [dict get $options -errorcode] 2]
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}
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if {$status != 0} {
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puts "Problem running the script :"
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puts $results
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return
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}
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} else {
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puts "The script run_gtkwave.tcl does not exist in $root_dir/scripts"
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}
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}
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proc main {} {
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variable root_dir
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# Set the reference directory to where the script is
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#set root_dir [file dirname [info script]]
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# Set the reference directory for source file relative paths (by default the value is script directory path)
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set root_dir "."
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# Use origin directory path location variable, if specified in the tcl shell
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if { [info exists ::root_dir_loc] } {
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set root_dir $::root_dir_loc
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}
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variable action "help"
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variable verbose false
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if { $::argc > 0 } {
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for {set i 0} {$i < $::argc} {incr i} {
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set option [string trim [lindex $::argv $i]]
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switch -regexp -- $option {
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"--root" { incr i; set root_dir [lindex $::argv $i] }
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"--help" { print_help }
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"help" { print_help }
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"clean" { set action "clean" }
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"sim" {incr i; set action "sim_[lindex $::argv $i]" }
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"--verbose" { set verbose true }
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"-v" { set verbose true }
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{pytest|cocotb|test} {set action "pytest"}
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{formal|verify|verification} {set action "formal"}
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{view} {set action "view"}
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default {
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if { [regexp {^-} $option] } {
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puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
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return 1
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}
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}
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}
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}
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} else {
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print_help
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}
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puts "Script started. The root dir is $root_dir. The action is: $action\n"
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switch -regexp -- $action {
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"clean" { do_clean $root_dir }
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{sim_icarus|^sim_$|sim_iverilog} { do_sim_icarus $root_dir $verbose}
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{sim_cocotb|pytest} { do_sim_pytest $root_dir $verbose}
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"formal" { do_formal $root_dir}
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"view" {do_view $root_dir}
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}
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}
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main
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}
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88
Help/presentation_examples/example1/scripts/run_gtkwave.tcl
Normal file
88
Help/presentation_examples/example1/scripts/run_gtkwave.tcl
Normal file
@@ -0,0 +1,88 @@
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# Tcl script for iverilog simulation
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namespace eval gtkwave {
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# Help information for this script
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proc print_help {} {
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variable script_file "run_gtkwave.tcl"
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puts "\nDescription:"
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puts "Runs the iverilog simulation.\n"
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puts "Syntax:"
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puts "$script_file"
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puts "$script_file \[action\] \[args\]"
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puts "Usage:"
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puts "Name Description"
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puts "-------------------------------------------------------------------------"
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puts "\[action\] Determine the action to be performed. Default value: help\n"
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puts " Current actions: help, clean\n"
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puts "\[args\] Arguments related to the action.\n"
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puts " --root <dir> changes the root reference for the project.\n"
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puts "-------------------------------------------------------------------------\n"
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exit 0
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}
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proc main {} {
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variable root_dir
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# Set the reference directory to where the script is
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#set root_dir [file dirname [info script]]
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# Set the reference directory for source file relative paths (by default the value is script directory path)
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set root_dir "."
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if { [info exists ::root_dir_loc] } {
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set root_dir $::root_dir_loc
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}
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if { $::argc > 0 } {
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set root_dir [lindex $::argv 0]
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}
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puts "Starting gtkwave. The root dir is: $root_dir"
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# variable root [file dirname [file normalize [info script]]]
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# variable root [file dirname [file dirname [info script]]]
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variable root $root_dir
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variable view_file $root/runs/sim/iverilog/counter_tb.vcd
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variable gtkwave_script $root/scripts/gtk_wave_all_signals.tcl
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proc run_view {res} {
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set name [file rootname $res]
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# set iverilog_args "$sim_iverilog::additional_options -g2012 -Wall -I $sim_iverilog::source_path -Y .sv -y $sim_iverilog::source_path -o $sim_iverilog::output_dir/$name.vvp $sim_iverilog::tb_path/$tb $sim_iverilog::sources_full_path"
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#set gtkwave_args "-S $gtkwave::gtkwave_script $gtkwave::view_file"
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set gtkwave_args "$gtkwave::view_file"
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#puts $gtkwave_args
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try {
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set results [exec gtkwave {*}$gtkwave_args]
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set status 0
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} trap CHILDSTATUS {results options} {
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set status [lindex [dict get $options -errorcode] 2]
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}
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if {$status != 0} {
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puts "Problem running gtkwave :"
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puts $results
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return
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}
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# output iverilog result
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puts $results
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}
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run_view $root_dir
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exit 0
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}
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# run main
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main
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}
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133
Help/presentation_examples/example1/scripts/run_iverilog.tcl
Normal file
133
Help/presentation_examples/example1/scripts/run_iverilog.tcl
Normal file
@@ -0,0 +1,133 @@
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# Tcl script for iverilog simulation
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namespace eval sim_iverilog {
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# Help information for this script
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proc print_help {} {
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variable script_file "run_iverilog.tcl"
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puts "\nDescription:"
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puts "Runs the iverilog simulation.\n"
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puts "Syntax:"
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puts "$script_file"
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puts "$script_file \[action\] \[args\]"
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puts "Usage:"
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puts "Name Description"
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puts "-------------------------------------------------------------------------"
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||||
puts "\[action\] Determine the action to be performed. Default value: help\n"
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||||
puts " Current actions: help, clean\n"
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||||
puts "\[args\] Arguments related to the action.\n"
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||||
puts " --root <dir> changes the root reference for the project.\n"
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puts "-------------------------------------------------------------------------\n"
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exit 0
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||||
}
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||||
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||||
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||||
proc main {} {
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variable root_dir
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# Set the reference directory to where the script is
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#set root_dir [file dirname [info script]]
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||||
|
||||
# Set the reference directory for source file relative paths (by default the value is script directory path)
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||||
set root_dir "."
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if { [info exists ::root_dir_loc] } {
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set root_dir $::root_dir_loc
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}
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||||
|
||||
if { $::argc > 0 } {
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set root_dir [lindex $::argv 0]
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}
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puts "Starting simulation using iverilog. The root dir is: $root_dir"
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# variable root [file dirname [file normalize [info script]]]
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# variable root [file dirname [file dirname [info script]]]
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variable root $root_dir
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variable source_path $root/src/verilog
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variable sources {example1.v}
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variable tb_path $root/tests/verilog
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||||
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||||
variable test_benches {example1_tb.v}
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||||
proc append_path {root list} {
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set l {}
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foreach f $list {
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lappend l $root/$f
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||||
}
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||||
return $l
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||||
}
|
||||
|
||||
variable sources_full_path [append_path $source_path $sources]
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||||
variable tb_full_path [append_path $tb_path $test_benches]
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||||
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||||
variable output_dir $root/runs/sim/iverilog
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||||
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||||
variable additional_options "-D VCD_DUMP"
|
||||
|
||||
proc run_sim {tb} {
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set name [file rootname $tb]
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||||
puts "Running test bench $name"
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||||
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||||
puts "Cleaning files..."
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||||
|
||||
# file delete [glob -nocomplain $sim_iverilog::output_dir/*]
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||||
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||||
puts "Recreating path..."
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||||
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||||
file mkdir $sim_iverilog::output_dir
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||||
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||||
set iverilog_args "$sim_iverilog::additional_options -g2012 -Wall -I $sim_iverilog::source_path -Y .sv -y $sim_iverilog::source_path -o $sim_iverilog::output_dir/$name.vvp $sim_iverilog::tb_path/$tb $sim_iverilog::sources_full_path"
|
||||
|
||||
|
||||
try {
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||||
set results [exec iverilog {*}$iverilog_args]
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||||
set status 0
|
||||
} trap CHILDSTATUS {results options} {
|
||||
set status [lindex [dict get $options -errorcode] 2]
|
||||
}
|
||||
|
||||
if {$status != 0} {
|
||||
puts "Problem running iverilog :"
|
||||
puts $results
|
||||
return
|
||||
}
|
||||
|
||||
# output iverilog result
|
||||
puts $results
|
||||
|
||||
set cwd [pwd]
|
||||
|
||||
puts "Running vvp..."
|
||||
|
||||
set vvp_cmd "vvp $name.vvp -lxt2"
|
||||
|
||||
cd $sim_iverilog::output_dir
|
||||
|
||||
#puts [pwd]
|
||||
set results [exec {*}$vvp_cmd]
|
||||
|
||||
# output vvp result
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||||
puts $results
|
||||
|
||||
cd $cwd
|
||||
|
||||
puts "All done..."
|
||||
|
||||
}
|
||||
|
||||
foreach tb $test_benches {
|
||||
run_sim $tb
|
||||
}
|
||||
|
||||
exit 0
|
||||
}
|
||||
|
||||
# run main
|
||||
|
||||
main
|
||||
|
||||
}
|
37
Help/presentation_examples/example1/src/verilog/example1.v
Normal file
37
Help/presentation_examples/example1/src/verilog/example1.v
Normal file
@@ -0,0 +1,37 @@
|
||||
`default_nettype none
|
||||
module example1 (
|
||||
input wire clk, // global clock
|
||||
input wire [7:0] edx,
|
||||
output reg strobe, // output strobe
|
||||
output wire [7:0] res
|
||||
);
|
||||
|
||||
localparam WIDTH=4;
|
||||
|
||||
reg[WIDTH-1:0] count = 0;
|
||||
|
||||
always_comb begin
|
||||
strobe = &count;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
count <= count + 1;
|
||||
end
|
||||
|
||||
|
||||
assign res = edx + 5;
|
||||
|
||||
endmodule
|
||||
|
||||
/*
|
||||
module top_module (
|
||||
input in1,
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||||
input in2,
|
||||
input in3,
|
||||
output out);
|
||||
|
||||
always_comb
|
||||
out = ~(in1 ^ in2) ^ in3;
|
||||
|
||||
endmodule
|
||||
*/
|
@@ -0,0 +1,39 @@
|
||||
`timescale 1ns/1ps
|
||||
`default_nettype none
|
||||
|
||||
module example1_tb ();
|
||||
|
||||
reg clk = 0;
|
||||
|
||||
initial forever #5 clk = !clk;
|
||||
|
||||
wire strobe;
|
||||
|
||||
example1 count (.clk(clk), .strobe(strobe));
|
||||
|
||||
|
||||
initial begin
|
||||
`ifdef VCD_DUMP
|
||||
$dumpfile("counter_tb.vcd");
|
||||
$dumpvars(0,example1_tb);
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
initial begin
|
||||
`ifdef END_TIME
|
||||
#`END_TIME $finish();
|
||||
`else
|
||||
#1000 $finish();
|
||||
`endif
|
||||
end
|
||||
|
||||
initial begin
|
||||
#500 $finish();
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (strobe) $display("Strobe");
|
||||
end
|
||||
|
||||
endmodule
|
@@ -0,0 +1,27 @@
|
||||
[tasks]
|
||||
bmc
|
||||
prove
|
||||
cover
|
||||
|
||||
[options]
|
||||
bmc: mode bmc
|
||||
prove: mode prove
|
||||
cover: mode cover
|
||||
bmc: depth 100
|
||||
|
||||
[engines]
|
||||
smtbmc
|
||||
#smtbmc z3
|
||||
#abc bmc3
|
||||
|
||||
|
||||
|
||||
[script]
|
||||
read -verific
|
||||
read -sv counter.v
|
||||
read -formal counter_formal.sv
|
||||
prep -top counter
|
||||
|
||||
[files]
|
||||
../src/verilog/counter.v
|
||||
counter_formal.sv
|
@@ -0,0 +1,48 @@
|
||||
`default_nettype none
|
||||
|
||||
module counter_formal (
|
||||
input wire clk, // global clock
|
||||
input wire reset, // synchronous reset signal
|
||||
(*anyseq*) input wire en, // enable signal
|
||||
input wire strobe, // output strobe
|
||||
input wire [counter.WIDTH-1:0] counter_reg
|
||||
|
||||
);
|
||||
|
||||
`ifdef VERIFIC
|
||||
internal_check: assert property (@(posedge clk)
|
||||
disable iff (reset)
|
||||
en && (counter_reg==11)|=>(counter_reg==10)) ;
|
||||
|
||||
decrease_enable_check: assert property (@(posedge clk)
|
||||
disable iff (reset || !en)
|
||||
(counter_reg >0 ) |=> (counter_reg == $past(counter_reg) - 1));
|
||||
|
||||
roll_enable_check: assert property (@(posedge clk)
|
||||
disable iff (reset || !en)
|
||||
(counter_reg == 0 ) |=> (counter_reg == counter.INITIAL_VALUE));
|
||||
|
||||
max_value_assert_check: assert property (
|
||||
@(posedge clk)
|
||||
(counter_reg <= counter.INITIAL_VALUE)
|
||||
);
|
||||
|
||||
cover_0: cover property(
|
||||
@(posedge clk)
|
||||
(counter_reg == 0)
|
||||
);
|
||||
|
||||
cover_2stb: cover property(
|
||||
@(posedge clk)
|
||||
(strobe == 1) |-> ##[+] (strobe == 1)
|
||||
);
|
||||
|
||||
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
bind counter counter_formal counter_f_inst(.*);
|
||||
|
||||
|
||||
//testing: assert property (@(posedge clk)(counter_reg==111)|=>(counter_reg==10));
|
Reference in New Issue
Block a user