struct

Help/presentation_examples/example1/tests/verilog/example1_tb.v

@@ -0,0 +1,39 @@
+`timescale 1ns/1ps
+`default_nettype none
+
+module example1_tb ();
+
+reg clk = 0;
+
+initial forever #5 clk = !clk;
+
+wire strobe;
+
+example1 count (.clk(clk), .strobe(strobe));
+
+
+initial begin
+`ifdef VCD_DUMP
+  $dumpfile("counter_tb.vcd");
+  $dumpvars(0,example1_tb);
+`endif
+end 
+
+
+initial begin
+`ifdef END_TIME
+    #`END_TIME $finish();
+`else
+    #1000 $finish();
+`endif
+end
+
+initial begin
+    #500 $finish();   
+end
+
+always @(posedge clk) begin
+    if (strobe) $display("Strobe");
+end
+
+endmodule