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Gamenight77
2025-05-02 15:51:18 +02:00
parent 0faab53c30
commit f5e73d7379
105 changed files with 707398 additions and 1 deletions
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4
Help/presentation_examples/led_walk/.gitignore vendored Normal file
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runs
.vscode
workspace.code-workspace
*.pyc

15
Help/presentation_examples/led_walk/constraints/blink_led.cst Normal file
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IO_LOC "leds[5]" 20;
IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[4]" 19;
IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[3]" 18;
IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[2]" 17;
IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" 16;
IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[0]" 15;
IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clk" 4;
IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8;

2
Help/presentation_examples/led_walk/constraints/blink_leds.sdc Normal file
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create_clock -name clk_27M -period 37.037 -waveform {0 18.518} [get_ports {clk}]

2
Help/presentation_examples/led_walk/project.bat Normal file
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@call c:\tools\oss-cad-suite\environment.bat
@tclsh scripts\project.tcl %*

20
Help/presentation_examples/led_walk/scripts/gtk_wave_all_signals.tcl Normal file
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puts "Starting TCL script"
#set path test1b_tb
#gtkwave::forceOpenTreeNode $path
set nfacs [ gtkwave::getNumFacs ]
puts "There are $nfacs signals"
set l [list]
for {set i 0} {$i < $nfacs } {incr i} {
set facname [ gtkwave::getFacName $i ]
set numdots [ expr {[llength [split $facname .]] - 1}]
# puts "$numdots"
if {$numdots == 1} {
lappend l "$facname"
puts "Added signal $facname"
}
}
set num_added [ gtkwave::addSignalsFromList $l ]
gtkwave::setZoomRangeTimes [ gtkwave::getMinTime ] [ gtkwave::getMaxTime ]
puts "Start time [ gtkwave::getMinTime ] end time: [ gtkwave::getMaxTime ]"

184
Help/presentation_examples/led_walk/scripts/project.tcl Normal file
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# Tcl launcher script for the project
namespace eval project_launcher {
# Help information for this script
proc print_help {} {
variable script_file "project.tcl"
puts "\nDescription:"
puts "Perform actions related to this project.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file \[action\] \[args\]"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[action\] Determine the action to be performed. Default value: help\n"
puts " Current actions: help, clean, sim, verify, test, view, elaborate\n"
puts "\[args\] Arguments related to the action.\n"
puts " --root <dir> changes the root reference for the project.\n"
puts "-------------------------------------------------------------------------\n"
exit 0
}
proc do_clean { root_dir } {
variable dir "$root_dir/runs"
puts "Cleaning all files in directory $dir...\n"
# Checking if the folder is empty to avoid error
if {[catch { glob "$dir/*" } result] != 1} {
file delete -force -- {*}[glob "$dir/*" ]
}
}
proc do_sim_icarus { root_dir verbose } {
# Checking if the folder is empty to avoid error
if {[file exists "$root_dir/scripts/run_iverilog.tcl"] == 1} {
#global root_dir_loc $root_dir
#source $root_dir/scripts/run_iverilog.tcl
try {
set results [exec tclsh $root_dir/scripts/run_iverilog.tcl $root_dir ]
set status 0
} trap CHILDSTATUS {results options} {
set status [lindex [dict get $options -errorcode] 2]
}
if {$status != 0} {
puts "Problem running the script :"
puts $results
return
}
if {[expr $verbose]} {
# output the result of the execution
puts $results
}
} else {
puts "The script run_iverilog.tcl does not exist in $root_dir/scripts"
}
}
proc do_sim_pytest { root_dir verbose } {
exec pytest $root_dir/tests/ >@stdout 2>@stderr
}
proc do_elaborate { root_dir } {
exec $root_dir/scripts/run_elaborate.bat
}
proc do_formal { root_dir } {
# We suppose that the sby file is meant to be run from the inside of the folder
# hence we cd there
if {[file pathtype $root_dir] != "absolute"} {
set root_dir "../$root_dir"
}
#set root_dir [file normalize $root_dir]
cd verification
#variable fname [glob -nocomplain $root_dir/verification/*.sby]
variable fname [glob -nocomplain *.sby]
if {[llength $fname]} {
set fname [lindex $fname 0]
puts "Using $fname file..."
exec sby -f $fname --prefix $root_dir/runs/verification/counter >@stdout 2>@stderr
} else {
puts "There are no .sby files present..."
cd ..
return
}
cd ..
}
proc do_view { root_dir } {
# Checking if the folder is empty to avoid error
if {[file exists "$root_dir/scripts/run_gtkwave.tcl"] == 1} {
try {
set results [exec tclsh $root_dir/scripts/run_gtkwave.tcl $root_dir ]
set status 0
} trap CHILDSTATUS {results options} {
set status [lindex [dict get $options -errorcode] 2]
}
if {$status != 0} {
puts "Problem running the script :"
puts $results
return
}
} else {
puts "The script run_gtkwave.tcl does not exist in $root_dir/scripts"
}
}
proc main {} {
variable root_dir
# Set the reference directory to where the script is
#set root_dir [file dirname [info script]]
# Set the reference directory for source file relative paths (by default the value is script directory path)
set root_dir "."
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::root_dir_loc] } {
set root_dir $::root_dir_loc
}
variable action "help"
variable verbose false
if { $::argc > 0 } {
for {set i 0} {$i < $::argc} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--root" { incr i; set root_dir [lindex $::argv $i] }
"--help" { print_help }
"help" { print_help }
"clean" { set action "clean" }
"sim" {incr i; set action "sim_[lindex $::argv $i]" }
"--verbose" { set verbose true }
"-v" { set verbose true }
{pytest|cocotb|test} {set action "pytest"}
{formal|verify|verification} {set action "formal"}
{view} {set action "view"}
{elaborate} {set action "elaborate"}
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
} else {
print_help
}
puts "Script started. The root dir is $root_dir. The action is: $action\n"
switch -regexp -- $action {
"clean" { do_clean $root_dir }
{sim_icarus|^sim_$|sim_iverilog} { do_sim_icarus $root_dir $verbose}
{sim_cocotb|pytest} { do_sim_pytest $root_dir $verbose}
"formal" { do_formal $root_dir}
"view" {do_view $root_dir}
"elaborate" {do_elaborate $root_dir}
}
}
main
}

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Help/presentation_examples/led_walk/scripts/run_elaborate.bat Normal file
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@echo off
rem https://github.com/YosysHQ/apicula
set name=led_walk
set file_name=src\verilog\counter.v src\verilog\%name%.v src\verilog\%name%_top.v
set constraints_file=constraints\blink_led.cst
yosys -p "read_verilog -sv %file_name%; synth_gowin -json runs\%name%_c.json"
set DEVICE=GW2AR-LV18QN88C8/I7
set BOARD=tangnano20k
nextpnr-himbaechel --json runs\%name%_c.json --write runs\pnr_%name%.json --device %DEVICE% --vopt cst=%constraints_file% --vopt family=GW2A-18C
gowin_pack -d %DEVICE% -o runs\%name%_c.fs runs\pnr_%name%.json
rem openfpgaloader -b %BOARD% blink_led_c.fs

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Help/presentation_examples/led_walk/scripts/run_gtkwave.tcl Normal file
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# Tcl script for iverilog simulation
namespace eval gtkwave {
# Help information for this script
proc print_help {} {
variable script_file "run_gtkwave.tcl"
puts "\nDescription:"
puts "Runs the iverilog simulation.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file \[action\] \[args\]"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[action\] Determine the action to be performed. Default value: help\n"
puts " Current actions: help, clean\n"
puts "\[args\] Arguments related to the action.\n"
puts " --root <dir> changes the root reference for the project.\n"
puts "-------------------------------------------------------------------------\n"
exit 0
}
proc main {} {
variable root_dir
# Set the reference directory to where the script is
#set root_dir [file dirname [info script]]
# Set the reference directory for source file relative paths (by default the value is script directory path)
set root_dir "."
if { [info exists ::root_dir_loc] } {
set root_dir $::root_dir_loc
}
if { $::argc > 0 } {
set root_dir [lindex $::argv 0]
}
puts "Starting gtkwave. The root dir is: $root_dir"
# variable root [file dirname [file normalize [info script]]]
# variable root [file dirname [file dirname [info script]]]
variable root $root_dir
variable view_file $root/runs/sim/iverilog/led_walk_tb.vcd
variable gtkwave_script $root/scripts/gtk_wave_all_signals.tcl
proc run_view {res} {
set name [file rootname $res]
# set iverilog_args "$sim_iverilog::additional_options -g2012 -Wall -I $sim_iverilog::source_path -Y .sv -y $sim_iverilog::source_path -o $sim_iverilog::output_dir/$name.vvp $sim_iverilog::tb_path/$tb $sim_iverilog::sources_full_path"
#set gtkwave_args "-S $gtkwave::gtkwave_script $gtkwave::view_file"
set gtkwave_args "$gtkwave::view_file"
#puts $gtkwave_args
try {
set results [exec gtkwave {*}$gtkwave_args]
set status 0
} trap CHILDSTATUS {results options} {
set status [lindex [dict get $options -errorcode] 2]
}
if {$status != 0} {
puts "Problem running gtkwave :"
puts $results
return
}
# output iverilog result
puts $results
}
run_view $root_dir
exit 0
}
# run main
main
}

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Help/presentation_examples/led_walk/scripts/run_iverilog.tcl Normal file
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# Tcl script for iverilog simulation
namespace eval sim_iverilog {
# Help information for this script
proc print_help {} {
variable script_file "run_iverilog.tcl"
puts "\nDescription:"
puts "Runs the iverilog simulation.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file \[action\] \[args\]"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[action\] Determine the action to be performed. Default value: help\n"
puts " Current actions: help, clean\n"
puts "\[args\] Arguments related to the action.\n"
puts " --root <dir> changes the root reference for the project.\n"
puts "-------------------------------------------------------------------------\n"
exit 0
}
proc main {} {
variable root_dir
# Set the reference directory to where the script is
#set root_dir [file dirname [info script]]
# Set the reference directory for source file relative paths (by default the value is script directory path)
set root_dir "."
if { [info exists ::root_dir_loc] } {
set root_dir $::root_dir_loc
}
if { $::argc > 0 } {
set root_dir [lindex $::argv 0]
}
puts "Starting simulation using iverilog. The root dir is: $root_dir"
# variable root [file dirname [file normalize [info script]]]
# variable root [file dirname [file dirname [info script]]]
variable root $root_dir
variable source_path $root/src/verilog
variable sources {led_walk.v}
variable tb_path $root/tests/verilog
variable test_benches {led_walk_tb.v}
proc append_path {root list} {
set l {}
foreach f $list {
lappend l $root/$f
}
return $l
}
variable sources_full_path [append_path $source_path $sources]
variable tb_full_path [append_path $tb_path $test_benches]
variable output_dir $root/runs/sim/iverilog
variable additional_options "-D VCD_DUMP"
proc run_sim {tb} {
set name [file rootname $tb]
puts "Running test bench $name"
puts "Cleaning files..."
# file delete [glob -nocomplain $sim_iverilog::output_dir/*]
puts "Recreating path..."
file mkdir $sim_iverilog::output_dir
set iverilog_args "$sim_iverilog::additional_options -g2012 -Wall -I $sim_iverilog::source_path -Y .sv -y $sim_iverilog::source_path -o $sim_iverilog::output_dir/$name.vvp $sim_iverilog::tb_path/$tb $sim_iverilog::sources_full_path"
try {
set results [exec iverilog {*}$iverilog_args]
set status 0
} trap CHILDSTATUS {results options} {
set status [lindex [dict get $options -errorcode] 2]
}
if {$status != 0} {
puts "Problem running iverilog :"
puts $results
return
}
# output iverilog result
puts $results
set cwd [pwd]
puts "Running vvp..."
set vvp_cmd "vvp $name.vvp -lxt2"
cd $sim_iverilog::output_dir
#puts [pwd]
set results [exec {*}$vvp_cmd]
# output vvp result
puts $results
cd $cwd
puts "All done..."
}
foreach tb $test_benches {
run_sim $tb
}
exit 0
}
# run main
main
}

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Help/presentation_examples/led_walk/scripts/run_load.bat Normal file
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@echo off
rem https://github.com/YosysHQ/apicula
set name=led_walk
set BOARD=tangnano20k
openfpgaloader -b %BOARD% runs\%name%_c.fs

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Help/presentation_examples/led_walk/src/verilog/counter.v Normal file
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`timescale 1ns/1ps
`default_nettype none
// Simple counter_reg with synchronous reset (and no load)
//
module counter #(
parameter WIDTH = 8,
parameter INITIAL_VALUE = 8'h0f
) (
input wire clk, // global clock
input wire reset, // synchronous reset signal
input wire en, // enable signal
output reg strobe // output strobe
);
initial strobe = 0;
reg[WIDTH-1:0] counter_reg = INITIAL_VALUE;
always @(posedge clk) begin
if (reset) begin
counter_reg <= INITIAL_VALUE;
end
else if (en) begin
strobe <= 0;
if (counter_reg == 0)
counter_reg <= INITIAL_VALUE;
else begin
if (counter_reg == 1)
strobe <= 1;
counter_reg <= counter_reg - 1;
end
end
end
`ifdef FORMAL
reg f_past_valid = 0;
always @* f_past_valid = !$initstate;
always @* begin
assume (counter_reg <= INITIAL_VALUE);
end
always @(posedge clk) begin
// if ($initstate) begin
// assume(counter_reg==INITIAL_VALUE);
// end
// if (!$initstate && $past(en)==1 && !$past(reset)) begin
if (f_past_valid && $past(en)==1 && !$past(reset)) begin
if (counter_reg < INITIAL_VALUE)
assert (counter_reg == $past(counter_reg) - 1);
else begin
assert(counter_reg == INITIAL_VALUE && $past(counter_reg)==0);
end
end
end
`endif
`ifdef VERIFIC
//internal_check: assert property (@(posedge clk)(counter_reg==11)|=>(counter_reg==10));
//assert property (@(posedge clk)(counter_reg==11 && en && !reset)|=>(counter_reg==10));
`endif
endmodule

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Help/presentation_examples/led_walk/src/verilog/led_walk.v Normal file
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`timescale 1ns/1ps
`default_nettype none
module led_walk #(
parameter CLK_SPEED = 27_000_000,
parameter NBLEDS = 5
)
(
input wire clk,
output reg [NBLEDS-1:0] led
);
wire strobe;
localparam ONE_HALF_S = CLK_SPEED / 2;
localparam ONE_S = CLK_SPEED ;
localparam TWO_S = CLK_SPEED *2;
localparam TIME = TWO_S;
localparam TIME_WIDTH = $clog2(TIME);
initial led = {NBLEDS{1'b1}};
counter #(.WIDTH(TIME_WIDTH), .INITIAL_VALUE(TIME)) counter_inst
(
.clk(clk),
.reset(1'b0),
.en(1'b1),
.strobe(strobe)
);
// State machine to cycle through LEDs
reg [$clog2(NBLEDS)-1:0] current_led; // Tracks the current LED index
always_ff @(posedge clk) begin
if (strobe) begin
// Turn off all LEDs and turn on the next one in the cycle
led <= {NBLEDS{1'b1}};
led[current_led] <= 1'b0;
// Move to the next LED in the cycle
if (current_led == NBLEDS - 1)
current_led <= 0;
else
current_led <= current_led + 1;
end
end
endmodule

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Help/presentation_examples/led_walk/src/verilog/led_walk_top.v Normal file
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module blink_top
(
input wire clk,
output wire [5:0] leds
);
led_walk #(
.CLK_SPEED(27_000_000),
.NBLEDS(6)
) lw_inst (
.clk(clk),
.led(leds)
);
endmodule

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Help/presentation_examples/led_walk/tests/verilog/led_walk_tb.v Normal file
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`timescale 1ns/1ps
`default_nettype none
module led_walk_tb ();
reg clk = 0;
initial forever #5 clk = !clk;
wire led[4];
blink #(.CLK_SPEED(20), .NBLEDS(4)) bl (.clk(clk),.led(led));
initial begin
`ifdef VCD_DUMP
$dumpfile("led_walk_tb.vcd");
$dumpvars(0,led_walk_tb);
`endif
end
initial begin
`ifdef END_TIME
#`END_TIME $finish();
`else
#1000 $finish();
`endif
end
initial begin
#500 $finish();
end
endmodule

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Help/presentation_examples/led_walk/verification/counter1.sby Normal file
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[tasks]
bmc
prove
cover
[options]
bmc: mode bmc
prove: mode prove
cover: mode cover
bmc: depth 100
[engines]
smtbmc
#smtbmc z3
#abc bmc3
[script]
read -verific
read -sv counter.v
read -formal counter_formal.sv
prep -top counter
[files]
../src/verilog/counter.v
counter_formal.sv

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Help/presentation_examples/led_walk/verification/counter_formal.sv Normal file
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`default_nettype none
module counter_formal (
input wire clk, // global clock
input wire reset, // synchronous reset signal
(*anyseq*) input wire en, // enable signal
input wire strobe, // output strobe
input wire [counter.WIDTH-1:0] counter_reg
);
`ifdef VERIFIC
internal_check: assert property (@(posedge clk)
disable iff (reset)
en && (counter_reg==11)|=>(counter_reg==10)) ;
decrease_enable_check: assert property (@(posedge clk)
disable iff (reset || !en)
(counter_reg >0 ) |=> (counter_reg == $past(counter_reg) - 1));
roll_enable_check: assert property (@(posedge clk)
disable iff (reset || !en)
(counter_reg == 0 ) |=> (counter_reg == counter.INITIAL_VALUE));
max_value_assert_check: assert property (
@(posedge clk)
(counter_reg <= counter.INITIAL_VALUE)
);
cover_0: cover property(
@(posedge clk)
(counter_reg == 0)
);
cover_2stb: cover property(
@(posedge clk)
(strobe == 1) |-> ##[+] (strobe == 1)
);
`endif
endmodule
bind counter counter_formal counter_f_inst(.*);
//testing: assert property (@(posedge clk)(counter_reg==111)|=>(counter_reg==10));