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forked from tanchou/Verilog
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Gamenight77
2025-05-02 15:51:18 +02:00
parent 0faab53c30
commit f5e73d7379
105 changed files with 707398 additions and 1 deletions

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@@ -1,5 +1,5 @@
`timescale 1ns / 1ps
// `default_nettype none
module tb_top_uart_rx_tx;
// Signaux