forked from tanchou/Verilog
uart_rx valid
This commit is contained in:
@@ -1,4 +1,4 @@
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module uart_rx
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module other_uart_rx
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#(
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parameter CLK_FRE = 27, //clock frequency(Mhz)
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parameter BAUD_RATE = 115200 //serial baud rate
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133
Semaine_4/UART/IP/verilog/other_tx.v
Normal file
133
Semaine_4/UART/IP/verilog/other_tx.v
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@@ -0,0 +1,133 @@
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module other_uart_tx
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#(
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parameter CLK_FRE = 27, //clock frequency(Mhz)
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parameter BAUD_RATE = 115200 //serial baud rate
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)
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(
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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input[7:0] tx_data, //data to send
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input tx_data_valid, //data to be sent is valid
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output reg tx_data_ready, //send ready
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output tx_pin //serial data output
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);
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//calculates the clock cycle for baud rate
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localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE;
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//state machine code
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localparam S_IDLE = 1;
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localparam S_START = 2;//start bit
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localparam S_SEND_BYTE = 3;//data bits
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localparam S_STOP = 4;//stop bit
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reg[2:0] state;
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reg[2:0] next_state;
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reg[15:0] cycle_cnt; //baud counter
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reg[2:0] bit_cnt;//bit counter
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reg[7:0] tx_data_latch; //latch data to send
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reg tx_reg; //serial data output
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assign tx_pin = tx_reg;
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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state <= S_IDLE;
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else
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state <= next_state;
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end
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always@(*)
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begin
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case(state)
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S_IDLE:
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if(tx_data_valid == 1'b1)
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next_state <= S_START;
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else
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next_state <= S_IDLE;
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S_START:
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if(cycle_cnt == CYCLE - 1)
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next_state <= S_SEND_BYTE;
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else
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next_state <= S_START;
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S_SEND_BYTE:
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
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next_state <= S_STOP;
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else
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next_state <= S_SEND_BYTE;
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S_STOP:
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if(cycle_cnt == CYCLE - 1)
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next_state <= S_IDLE;
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else
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next_state <= S_STOP;
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default:
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next_state <= S_IDLE;
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endcase
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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tx_data_ready <= 1'b0;
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end
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else if(state == S_IDLE)
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if(tx_data_valid == 1'b1)
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tx_data_ready <= 1'b0;
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else
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tx_data_ready <= 1'b1;
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else if(state == S_STOP && cycle_cnt == CYCLE - 1)
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tx_data_ready <= 1'b1;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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tx_data_latch <= 8'd0;
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end
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else if(state == S_IDLE && tx_data_valid == 1'b1)
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tx_data_latch <= tx_data;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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bit_cnt <= 3'd0;
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end
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else if(state == S_SEND_BYTE)
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if(cycle_cnt == CYCLE - 1)
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bit_cnt <= bit_cnt + 3'd1;
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else
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bit_cnt <= bit_cnt;
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else
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bit_cnt <= 3'd0;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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cycle_cnt <= 16'd0;
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else if((state == S_SEND_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
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cycle_cnt <= 16'd0;
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else
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cycle_cnt <= cycle_cnt + 16'd1;
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end
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always@(posedge clk or negedge rst_n)
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begin
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if(rst_n == 1'b0)
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tx_reg <= 1'b1;
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else
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case(state)
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S_IDLE,S_STOP:
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tx_reg <= 1'b1;
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S_START:
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tx_reg <= 1'b0;
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S_SEND_BYTE:
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tx_reg <= tx_data_latch[bit_cnt];
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default:
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tx_reg <= 1'b1;
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endcase
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end
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endmodule
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@@ -1,3 +1,3 @@
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@echo off
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echo === Lancement de GTKWave ===
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gtkwave runs/uart_loopback.vcd
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gtkwave runs/uart_rx.vcd
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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
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set OUT=runs/sim.vvp
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:: Top-level testbench module
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set TOP=tb_uart_tx
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set TOP=tb_uart_rx
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:: Répertoires contenant des fichiers .v
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set DIRS=src/verilog tests/verilog IP/verilog
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145
Semaine_4/UART/src/verilog/uart_rx.v
Normal file
145
Semaine_4/UART/src/verilog/uart_rx.v
Normal file
@@ -0,0 +1,145 @@
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module uart_rx #(
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parameter CLK_FREQ = 27_000_000,
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parameter BAUD_RATE = 115200
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)(
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input clk, //clock input
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input rst_p, //asynchronous reset input, high active
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input rx_enable, //data receiver module ready
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input rx_pin, //serial data input
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output reg[7:0] rx_data, //received serial data
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output reg rx_received //received serial data is valid
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);
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localparam CYCLE = CLK_FREQ / BAUD_RATE;
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//state machine code
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localparam S_IDLE = 1;
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localparam S_START = 2; //start bit
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localparam S_REC_BYTE = 3; //data bits
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localparam S_STOP = 4; //stop bit
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localparam S_DATA = 5;
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reg[2:0] state;
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reg[2:0] next_state;
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reg rx_d0; //delay 1 clock for rx_pin
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reg rx_d1; //delay 1 clock for rx_d0
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wire rx_negedge; //negedge of rx_pin
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reg[7:0] rx_bits; //temporary storage of received data
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reg[15:0] cycle_cnt; //baud counter
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reg[2:0] bit_cnt; //bit counter
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assign rx_negedge = rx_d1 && ~rx_d0; // Front déscendant
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always@(posedge clk or posedge rst_p) // Filtrage du signial
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begin
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if(rst_p == 1'b1)begin
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rx_d0 <= 1'b0;
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rx_d1 <= 1'b0;
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end else begin
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rx_d0 <= rx_pin;
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rx_d1 <= rx_d0;
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end
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end
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always@(posedge clk or posedge rst_p)begin // Compteur d'etat
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if(rst_p == 1'b1)
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state <= S_IDLE;
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else
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state <= next_state;
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end
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always@(*)begin
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case(state)
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S_IDLE:
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if(rx_negedge) // Detection du start bit
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next_state = S_START;
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else
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next_state = S_IDLE;
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S_START:
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if(cycle_cnt == CYCLE - 1) //one data cycle
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next_state = S_REC_BYTE;
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else
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next_state = S_START;
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S_REC_BYTE:
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data
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next_state = S_STOP;
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else
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next_state = S_REC_BYTE;
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S_STOP:
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if(cycle_cnt == CYCLE/2 - 1) //half bit cycle,to avoid missing the next byte receiver
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next_state = S_DATA;
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else
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next_state = S_STOP;
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S_DATA:
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if(rx_enable) //data receive complete
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next_state = S_IDLE;
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else
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next_state = S_DATA;
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default:
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next_state = S_IDLE;
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endcase
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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rx_received <= 1'b0;
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else if(state == S_STOP && next_state != state)
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rx_received <= 1'b1;
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else if(state == S_DATA && rx_enable)
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rx_received <= 1'b0;
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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rx_data <= 8'd0;
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else if(state == S_STOP && next_state != state)
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rx_data <= rx_bits;//latch received data
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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begin
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bit_cnt <= 3'd0;
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end
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else if(state == S_REC_BYTE)
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if(cycle_cnt == CYCLE - 1)
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bit_cnt <= bit_cnt + 3'd1;
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else
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bit_cnt <= bit_cnt;
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else
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bit_cnt <= 3'd0;
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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cycle_cnt <= 16'd0;
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else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
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cycle_cnt <= 16'd0;
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else
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cycle_cnt <= cycle_cnt + 16'd1;
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end
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//receive serial data bit data
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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rx_bits <= 8'd0;
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else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
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rx_bits[bit_cnt] <= rx_pin;
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else
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rx_bits <= rx_bits;
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end
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endmodule
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67
Semaine_4/UART/tests/verilog/tb_uart_rx.v
Normal file
67
Semaine_4/UART/tests/verilog/tb_uart_rx.v
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@@ -0,0 +1,67 @@
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`timescale 1ns / 1ps
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module tb_uart_rx;
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reg clk = 0;
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reg rx;
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reg [7:0] data_in;
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reg [7:0] data_out;
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reg tx_data_valid;
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reg tx_data_ready;
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reg rx_received;
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wire rx_enable = 1'b1; // Enable the receiver
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localparam CLK_FREQ = 27_000_000;
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localparam BAUD_RATE = 115_200;
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localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
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localparam CLK_PERIOD_NS = 1000000000 / CLK_FREQ;
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other_uart_tx tx_instance (
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.clk(clk),
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.tx_pin(rx),
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.tx_data(data_in),
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.tx_data_valid(tx_data_valid),
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.tx_data_ready(tx_data_ready),
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.rst_n(1'b1)
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);
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uart_rx #(
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.CLK_FREQ(CLK_FREQ),
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.BAUD_RATE(BAUD_RATE)
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) rx_instance (
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.clk(clk),
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.rx_pin(rx),
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.rx_data(data_out),
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.rx_received(rx_received),
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.rx_enable(rx_enable)
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);
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always #(CLK_PERIOD_NS/2) clk = ~clk;
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initial begin
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$dumpfile("runs/uart_rx.vcd");
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$dumpvars(0, tb_uart_rx);
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$display("======== Start UART RX test =========");
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#100;
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data_in = 8'd123; // Data to send
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wait(tx_data_ready); // Wait for the transmitter to be ready
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#1; // Small delay to ensure the data is latched
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tx_data_valid = 1'b1; // Indicate that the data is valid
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wait(tx_data_ready == 0);
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tx_data_valid = 1'b0; // Clear the valid signal
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wait(rx_received); // Wait for the receiver to receive the data
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$display("Data sent: %d", data_in);
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$display("Data received: %d", data_out); // Display the received data
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$display("======== END UART RX test =========");
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$finish;
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end
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endmodule
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@@ -13,7 +13,7 @@ module tb_uart_tx;
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always #18.5 clk = ~clk;
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uart_rx rx_instance(
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other_uart_rx rx_instance(
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.clk(clk),
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.rx_pin(tx), // tx is connected to rx for testing
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.rst_n(1'b1),
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@@ -38,6 +38,8 @@ module tb_uart_tx;
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$dumpfile("runs/uart_tx.vcd");
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$dumpvars(0, tb_uart_tx);
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$display("======== Start UART TX test =========");
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#100;
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data_in <= 8'd234; // 234
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@@ -66,6 +68,8 @@ module tb_uart_tx;
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$display("Data received: %d", data_out); // Afficher la valeur recu
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$display("Data expected: %d", data_in); // Afficher la valeur envoyee
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$display("======== END UART TX test =========");
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#1000;
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$stop;
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end
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