uart_rx valid

2025-05-05 09:51:23 +02:00
parent c9a5fba97e
commit fc48941459
7 changed files with 353 additions and 4 deletions
--- a/Semaine_4/UART/IP/verilog/other_rx.v
+++ b/Semaine_4/UART/IP/verilog/other_rx.v
@@ -1,4 +1,4 @@
-module uart_rx
+module other_uart_rx
 #(
 	parameter CLK_FRE = 27,      //clock frequency(Mhz)
 	parameter BAUD_RATE = 115200 //serial baud rate