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uart_rx valid

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Gamenight77
2025-05-05 09:51:23 +02:00
parent c9a5fba97e
commit fc48941459
7 changed files with 353 additions and 4 deletions
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2
Semaine_4/UART/scripts/simulate.bat
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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=tb_uart_tx
set TOP=tb_uart_rx
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog