uart_rx valid

Semaine_4/UART/tests/verilog/tb_uart_rx.v

@@ -0,0 +1,67 @@
+`timescale 1ns / 1ps
+
+module tb_uart_rx;
+
+    reg clk = 0;
+    reg rx;  
+    reg [7:0] data_in;
+    reg [7:0] data_out;
+
+    reg tx_data_valid;
+    reg tx_data_ready;
+
+    reg rx_received;
+    wire rx_enable = 1'b1; // Enable the receiver
+
+    localparam CLK_FREQ = 27_000_000;
+    localparam BAUD_RATE = 115_200;
+    localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE; 
+    localparam CLK_PERIOD_NS = 1000000000 / CLK_FREQ; 
+
+    other_uart_tx tx_instance (
+        .clk(clk),
+        .tx_pin(rx),
+        .tx_data(data_in),
+        .tx_data_valid(tx_data_valid),
+        .tx_data_ready(tx_data_ready),
+        .rst_n(1'b1)
+    );
+
+    uart_rx #(
+        .CLK_FREQ(CLK_FREQ),
+        .BAUD_RATE(BAUD_RATE)
+    ) rx_instance (
+        .clk(clk),
+        .rx_pin(rx),
+        .rx_data(data_out),
+        .rx_received(rx_received),
+        .rx_enable(rx_enable)
+    );
+
+    always #(CLK_PERIOD_NS/2) clk = ~clk;
+
+    initial begin
+        $dumpfile("runs/uart_rx.vcd");
+        $dumpvars(0, tb_uart_rx);
+        $display("======== Start UART RX test =========");
+        #100; 
+
+        data_in = 8'd123; // Data to send
+        wait(tx_data_ready); // Wait for the transmitter to be ready
+        #1; // Small delay to ensure the data is latched
+
+        tx_data_valid = 1'b1; // Indicate that the data is valid
+        
+        wait(tx_data_ready == 0);
+
+        tx_data_valid = 1'b0; // Clear the valid signal
+
+        wait(rx_received); // Wait for the receiver to receive the data
+
+        $display("Data sent: %d", data_in);
+        $display("Data received: %d", data_out); // Display the received data
+
+        $display("======== END UART RX test =========");
+        $finish;
+    end
+endmodule

Semaine_4/UART/tests/verilog/tb_uart_tx.v

@@ -13,7 +13,7 @@ module tb_uart_tx;
 
     always #18.5 clk = ~clk;
 
-    uart_rx rx_instance(
+    other_uart_rx rx_instance(
         .clk(clk),
         .rx_pin(tx), // tx is connected to rx for testing
         .rst_n(1'b1),
@@ -38,6 +38,8 @@ module tb_uart_tx;
         $dumpfile("runs/uart_tx.vcd");
         $dumpvars(0, tb_uart_tx);
 
+        $display("======== Start UART TX test =========");
+
         #100;
 
         data_in <= 8'd234;   // 234
@@ -66,6 +68,8 @@ module tb_uart_tx;
         $display("Data received: %d", data_out); // Afficher la valeur recu
         $display("Data expected: %d", data_in); // Afficher la valeur envoyee
 
+        $display("======== END UART TX test =========");
+
         #1000;
         $stop;
     end