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uart_rx valid

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Gamenight77
2025-05-05 09:51:23 +02:00
parent c9a5fba97e
commit fc48941459
7 changed files with 353 additions and 4 deletions
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6
Semaine_4/UART/tests/verilog/tb_uart_tx.v
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@@ -13,7 +13,7 @@ module tb_uart_tx;
always #18.5 clk = ~clk;
uart_rx rx_instance(
other_uart_rx rx_instance(
.clk(clk),
.rx_pin(tx), // tx is connected to rx for testing
.rst_n(1'b1),
@@ -38,6 +38,8 @@ module tb_uart_tx;
$dumpfile("runs/uart_tx.vcd");
$dumpvars(0, tb_uart_tx);
$display("======== Start UART TX test =========");
#100;
data_in <= 8'd234; // 234
@@ -66,6 +68,8 @@ module tb_uart_tx;
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
$display("======== END UART TX test =========");
#1000;
$stop;
end