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forked from tanchou/Verilog

5 Commits

Author SHA1 Message Date
3569b55925 Refactor project scripts for Windows and Linux: update paths and create new scripts for build, clean, simulate, and GTKWave functionalities. 2025-05-15 09:26:34 +02:00
Gamenight77
861c9869f5 Add DHT11 interface and UART integration for ultrasonic sensor project
- Created DHT11 interface in Verilog to handle communication with DHT11 sensor.
- Implemented LED control logic to indicate sensor status and data readiness.
- Added project scripts for building, cleaning, and simulating the design.
- Established constraints for FPGA pin assignments.
- Developed testbench for DHT11 UART communication.
- Updated README files to reflect project functionality and commands.
2025-05-14 14:40:16 +02:00
Gamenight77
6a5b90c8d1 Refactor DHT11 interface: change output wires to registers for data ready, busy, and error signals 2025-05-14 10:31:48 +02:00
Gamenight77
2a153aa1eb Enhance DHT11 interface: add start signal and busy output, improve FSM for better data handling 2025-05-14 10:27:46 +02:00
Gamenight77
1d6677d67d Init du DHT11 Interface 2025-05-14 09:22:07 +02:00