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Verilog_Louis
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Gamenight77
434381e9b6
Refactor DHT11 module and testbench: update timing parameters, adjust state machine, and correct simulation script paths
2025-05-21 18:11:28 +02:00
Louis TANCHOU
cbebf620d5
Add DHT11 interface and model, update testbench and scripts for simulation
2025-05-20 15:55:21 +02:00