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verlan
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Verilog_Louis
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0b764026a1e59826963975a7329d6fc6dfff3149
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4 Commits
Author
SHA1
Message
Date
Louis TANCHOU
ebe6cefda4
Update S4 Uart FIFO
2025-06-05 15:59:12 +02:00
Gamenight77
e124c7c0c4
Bloquer a cause du tx
2025-05-13 12:22:50 +02:00
Gamenight77
e086ba8ef0
Loopback fifo fonctionne mais avec 3 valeur de décalage
2025-05-09 11:39:40 +02:00
Gamenight77
86d4f5ddd2
rx fifo et tx fifo on l'air de fonctionner lors des testbenchs
2025-05-06 10:59:08 +02:00