verlan/Verilog_Louis
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25 Commits 1 Branch 0 Tags
11b14ced36021b7a62f4b1e8a3de218e8a7e790c
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3 Commits

Author SHA1 Message Date
Gamenight77
11b14ced36 Update Projet_esp32.txt: add architecture diagram and detailed descriptions for UART modules 2025-04-22 16:38:00 +02:00
Gamenight77
574ace75ef Readme 2025-04-22 14:32:34 +02:00
Gamenight77
3bb56e2f57 Init et début de réflexion sur le projet 2025-04-22 09:56:06 +02:00