This website requires JavaScript.
Explore
Help
Sign In
verlan
/
Verilog_Louis
Watch
1
Star
0
Fork
0
You've already forked Verilog_Louis
forked from
tanchou/Verilog
Code
Pull Requests
Activity
103
Commits
1
Branch
0
Tags
168431849bd565859a14b79169ab9ec7a9b522c4
Commit Graph
2 Commits
Author
SHA1
Message
Date
Gamenight77
abef18227c
Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality
2025-05-07 09:46:43 +02:00
Gamenight77
1ca3456ab8
Création de la structure du uart fifo
2025-05-06 09:42:26 +02:00