verlan/Verilog_Louis
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1d39c68b5c05663af84d7b0f7a23984721410f05
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2 Commits

Author SHA1 Message Date
Gamenight77
1d39c68b5c Refactor uart_tx module to implement FIFO functionality with write and read pointers 2025-05-05 15:29:45 +02:00
Gamenight77
7156abf4e7 Add UART TX module and testbench, update scripts and constraints 2025-05-05 15:23:44 +02:00