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verlan
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Verilog_Louis
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286ba6b33c226fe235ee40ddb3b5a5cb7f6b759e
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Gamenight77
8641f618f0
Refactor uart_top module: streamline code structure and improve readability by removing unused variables and simplifying instantiation
2025-04-22 15:44:04 +02:00
Gamenight77
3bb56e2f57
Init et début de réflexion sur le projet
2025-04-22 09:56:06 +02:00