verlan/Verilog_Louis
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89 Commits 1 Branch 0 Tags
434381e9b6da6f4a61c300d417daf3ba8ab6f42b
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2 Commits

Author SHA1 Message Date
Gamenight77
aaebf22d48 Tb for fifo working fine 2025-05-06 09:14:59 +02:00
Gamenight77
7156abf4e7 Add UART TX module and testbench, update scripts and constraints 2025-05-05 15:23:44 +02:00