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forked from tanchou/Verilog
Commit Graph

6 Commits

Author SHA1 Message Date
Gamenight77
e66a464812 Sa a l'air de fonctionner 2025-05-16 10:34:32 +02:00
Gamenight77
b7d184d02f Gros patch sur la fifo et rx fifo pour gagner des tick d'horloge, uart comand fonctionne toujours pas 2025-05-13 10:21:28 +02:00
Gamenight77
99e259f672 MAJ FIFO -> turn wire rd_data into register 2025-05-09 10:27:13 +02:00
Gamenight77
aaebf22d48 Tb for fifo working fine 2025-05-06 09:14:59 +02:00
Gamenight77
1d39c68b5c Refactor uart_tx module to implement FIFO functionality with write and read pointers 2025-05-05 15:29:45 +02:00
Gamenight77
7156abf4e7 Add UART TX module and testbench, update scripts and constraints 2025-05-05 15:23:44 +02:00