verlan/Verilog_Louis
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92 Commits 1 Branch 0 Tags
4c3e40b26658b7d16dca634390f0ab49ea85a2e6
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2 Commits

Author SHA1 Message Date
Gamenight77
abef18227c Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality 2025-05-07 09:46:43 +02:00
Gamenight77
1ca3456ab8 Création de la structure du uart fifo 2025-05-06 09:42:26 +02:00