1
0
forked from tanchou/Verilog
Commit Graph

3 Commits

Author SHA1 Message Date
Gamenight77
65cf0e8232 Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading. 2025-04-17 18:00:54 +02:00
Gamenight77
897f829e40 Refactor ultrasonic_fpga module: update distance output and state handling; add top_ultrason_uart module for integration with UART and ultrasonic sensor 2025-04-17 13:02:47 +02:00
Gamenight77
55f9161dfa Add UART transmitter module and testbench
- Implemented the uart_tx module for UART transmission with configurable clock frequency and baud rate.
- Added a testbench (uart_tx_tb) to verify the functionality of the uart_tx module, including signal generation for start, data, and clock.
- Created a backup of the previous testbench (uart_tx_tb_old) for reference.
2025-04-17 10:56:16 +02:00