This website requires JavaScript.
Explore
Help
Sign In
verlan
/
Verilog_Louis
Watch
1
Star
0
Fork
0
You've already forked Verilog_Louis
forked from
tanchou/Verilog
Code
Pull Requests
Activity
17
Commits
1
Branch
0
Tags
65cf0e8232044577f1d95b44bce1f35560db0077
Commit Graph
2 Commits
Author
SHA1
Message
Date
Gamenight77
65cf0e8232
Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.
2025-04-17 18:00:54 +02:00
Gamenight77
897f829e40
Refactor ultrasonic_fpga module: update distance output and state handling; add top_ultrason_uart module for integration with UART and ultrasonic sensor
2025-04-17 13:02:47 +02:00