This website requires JavaScript.
Explore
Help
Sign In
verlan
/
Verilog_Louis
Watch
1
Star
0
Fork
0
You've already forked Verilog_Louis
forked from
tanchou/Verilog
Code
Pull Requests
Activity
16
Commits
1
Branch
0
Tags
897f829e40c06bb7e79bbc9786cdee6a2b7c56f6
Commit Graph
1 Commits
Author
SHA1
Message
Date
Gamenight77
897f829e40
Refactor ultrasonic_fpga module: update distance output and state handling; add top_ultrason_uart module for integration with UART and ultrasonic sensor
2025-04-17 13:02:47 +02:00