verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity
95 Commits 1 Branch 0 Tags
92144d315eb0061da6e4ce27d1a180372a241a39
Commit Graph

2 Commits

Author SHA1 Message Date
Gamenight77
abef18227c Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality 2025-05-07 09:46:43 +02:00
Gamenight77
1ca3456ab8 Création de la structure du uart fifo 2025-05-06 09:42:26 +02:00