verlan/Verilog_Louis
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85 Commits 1 Branch 0 Tags
9755b1b0a301df58b1b22b57a4e7e5a8872e0be5
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2 Commits

Author SHA1 Message Date
Gamenight77
aaebf22d48 Tb for fifo working fine 2025-05-06 09:14:59 +02:00
Gamenight77
7156abf4e7 Add UART TX module and testbench, update scripts and constraints 2025-05-05 15:23:44 +02:00