verlan/Verilog_Louis
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63 Commits 1 Branch 0 Tags
99e259f672ea5d30bbf8af5992aab921183f5cc4
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2 Commits

Author SHA1 Message Date
Gamenight77
83c40bee28 Fix build script and update state machine in UART loopback module 2025-05-07 10:39:52 +02:00
Gamenight77
ec1c69cf8f Implement UART and ultrasonic sensor integration with FIFO for data transmission 2025-05-07 10:27:17 +02:00