This website requires JavaScript.
Explore
Help
Sign In
verlan
/
Verilog_Louis
Watch
1
Star
0
Fork
0
You've already forked Verilog_Louis
forked from
tanchou/Verilog
Code
Pull Requests
Activity
54
Commits
1
Branch
0
Tags
abef18227c790ff7bf7ceee7502d487fb9692460
Commit Graph
2 Commits
Author
SHA1
Message
Date
Gamenight77
8641f618f0
Refactor uart_top module: streamline code structure and improve readability by removing unused variables and simplifying instantiation
2025-04-22 15:44:04 +02:00
Gamenight77
3bb56e2f57
Init et début de réflexion sur le projet
2025-04-22 09:56:06 +02:00