verlan/Verilog_Louis
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65 Commits 1 Branch 0 Tags
e086ba8ef0d87887fe9a3cc31c8162260de993b1
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2 Commits

Author SHA1 Message Date
Gamenight77
a792f85adf loopback fonctionne avec le rxuartlite 2025-05-09 09:15:28 +02:00
Gamenight77
f990a6f6d3 Fix UART RX module instantiation and update build script for correct file references 2025-05-07 11:07:42 +02:00