verlan/Verilog_Louis
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73 Commits 1 Branch 0 Tags
e124c7c0c4bd4516aec9ff4fe9b731ac8a34a5e9
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2 Commits

Author SHA1 Message Date
Gamenight77
a792f85adf loopback fonctionne avec le rxuartlite 2025-05-09 09:15:28 +02:00
Gamenight77
f990a6f6d3 Fix UART RX module instantiation and update build script for correct file references 2025-05-07 11:07:42 +02:00