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verlan
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Verilog_Louis
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e124c7c0c4bd4516aec9ff4fe9b731ac8a34a5e9
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Gamenight77
abef18227c
Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality
2025-05-07 09:46:43 +02:00
Gamenight77
1ca3456ab8
Création de la structure du uart fifo
2025-05-06 09:42:26 +02:00