Gamenight77
e66a464812
Sa a l'air de fonctionner
2025-05-16 10:34:32 +02:00
Gamenight77
861c9869f5
Add DHT11 interface and UART integration for ultrasonic sensor project
...
- Created DHT11 interface in Verilog to handle communication with DHT11 sensor.
- Implemented LED control logic to indicate sensor status and data readiness.
- Added project scripts for building, cleaning, and simulating the design.
- Established constraints for FPGA pin assignments.
- Developed testbench for DHT11 UART communication.
- Updated README files to reflect project functionality and commands.
2025-05-14 14:40:16 +02:00
Gamenight77
6a5b90c8d1
Refactor DHT11 interface: change output wires to registers for data ready, busy, and error signals
2025-05-14 10:31:48 +02:00
Gamenight77
2a153aa1eb
Enhance DHT11 interface: add start signal and busy output, improve FSM for better data handling
2025-05-14 10:27:46 +02:00
Gamenight77
1d6677d67d
Init du DHT11 Interface
2025-05-14 09:22:07 +02:00
Gamenight77
e124c7c0c4
Bloquer a cause du tx
2025-05-13 12:22:50 +02:00
Gamenight77
d1f907f7b6
Remove unnecessary IDE configuration files from the Python test directory
2025-05-13 10:21:47 +02:00
Gamenight77
b7d184d02f
Gros patch sur la fifo et rx fifo pour gagner des tick d'horloge, uart comand fonctionne toujours pas
2025-05-13 10:21:28 +02:00
Gamenight77
cca81f4db5
Fix formatting and update LED assignment in top_uart_ultrason_command module
2025-05-12 20:40:21 +02:00
Gamenight77
2cb68ce0d1
Debg compliqué
2025-05-12 15:34:02 +02:00
Gamenight77
790b85841b
Refactor UART testbench for ultrasonic commands: improve readability and organization of code structure
2025-05-12 13:24:58 +02:00
Gamenight77
30bbe27510
ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer
2025-05-12 12:15:52 +02:00
Gamenight77
e086ba8ef0
Loopback fifo fonctionne mais avec 3 valeur de décalage
2025-05-09 11:39:40 +02:00
