`timescale 1ns/1ps
`default_nettype none

module counter_tb ();

reg clk = 0;

initial forever #5 clk = !clk;

wire strobe;

reg reset = 1'b0;
reg en = 1'b1;

counter #(.WIDTH(8),.INITIAL_VALUE(15)) count (.clk(clk),.en(en), .reset(reset), .strobe(strobe));


initial begin
`ifdef VCD_DUMP
  $dumpfile("counter_tb.vcd");
  $dumpvars(0,counter_tb);
`endif
end 


initial begin
`ifdef END_TIME
    #`END_TIME $finish();
`else
    #1000 $finish();
`endif
end

initial begin
    @(posedge clk) reset = 1;
    @(posedge clk) reset = 0;
    en = 1;
    #400;
    @(posedge clk) en = 0;    
    #50;
    @(posedge clk) en = 1;
    #500 $finish();   
end

always @(posedge clk) begin
    if (strobe) $display("Strobe");
end

endmodule